scispace - formally typeset
Search or ask a question

Showing papers on "Electronic packaging published in 1985"


01 Jan 1985
TL;DR: The proceedings of the Symposium on electronic packaging materials science as discussed by the authors included overviews as well as papers which addressed levels of packaging and interconnection technologies for electronic systems are becoming an increasingly important part of these systems in terms of their cost, functionality, and complexity.
Abstract: This volume is the proceedings of the symposia on electronic packaging materials science. The symposium included overviews as well as papers which addressed levels of packaging. The packaging and interconnection technologies for electronic systems are becoming an increasingly important part of these systems in terms of their cost, functionality, and complexity. This trend is being driven by system trends toward higher density, higher speed, and higher thermal dissipation. The nature of these trends, and their impact on the demands placed on the materials are covered. New processes for depositing, etching and promoting interfacial adhesion are described. Particular materials issues associated with interconnection on the IC, from the IC to its package and between ICs are covered. The authors have dealt with issues particular to the packaging of Ga As and optoelectronic circuits.

142 citations


Journal ArticleDOI
M. Mahalingam1
01 Sep 1985
TL;DR: In this paper, thermal management at device level packaging involves efficient and cost-effective removal of dissipated thermal energy from the device to assure its reliable performance over the long term, which will mean making such devices possible close to the natural limits set by thermal physics.
Abstract: Thermal management at device level packaging involves efficient and cost-effective removal of dissipated thermal energy from the device to assure its reliable performance over the long term. In the context of very high levels of integration of future ICs, thermal management will mean making such devices possible close to the natural limits set by thermal physics. This paper will present trends in important parameters and discuss solutions through examples.

116 citations


Journal ArticleDOI
H. Murano1, T. Watari1
01 Dec 1985
TL;DR: The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle as discussed by the authors.
Abstract: Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.

95 citations


Proceedings ArticleDOI
29 May 1985
TL;DR: In this paper, an electronic device package is made by first making in a stencil member an opening (11) in the shape of a closed loop that surrounds an inner portion (13) of the stencil members.
Abstract: An electronic device package is made by first making in a stencil member (11) an opening (12) in the shape of a closed loop that surrounds an inner portion (13) of the stencil member. The closed loop is a continuous open ing except for a plurality of web members (15), each of which extends across the opening to secure the inner stencil portion to the remainder of the stencil member. A glass slurry (7) is forced through the opening of the stencil member onto a first substrate (18) so as to form on the substrate a substantially, closed loop of glass slurry, which is thereafter glazed to form a glass loop (32) bonded to the first substrate. The first substrate is used as cover plate and placed over a second substrate (24) containing an electronic device (23) such that the glass loop surrounds the electronic device and contacts the second substrate along its entire length. The glass is heated sufficiently to soften it and cause it to bond to the second substrate as well as the first substrate. Cooling of the glass loop develops continuous hermetic seals to both first and second substrate, thereby to isolate the electronic device from the external environment.

47 citations


Proceedings ArticleDOI
01 Jan 1985
TL;DR: In this paper, the cell structure is shown in Figure 1, where the first layer polycide forms the wordline and the second layer poly-Si, which forms the storage node, is extended over its own word line and the next wordline.
Abstract: pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the

29 citations


Book
01 Jan 1985

28 citations


Patent
19 Mar 1985
TL;DR: In this paper, a static dissipative elastomeric outer coating for an electronic package composite is described, which is characterized by its superior abrasion resistant and electrical properties.
Abstract: The invention features a static dissipative elastomeric outer coating for an electronic package composite. The coating is characterized by its superior abrasion resistant and electrical properties. The coating chemically bonds with the conductive layer and has superior static dissipative qualities characterized by a surface resistivity in the range of between 105 and 1011 ohms per square.

20 citations



Patent
21 Jun 1985
TL;DR: In this article, a composite body that is electrically insulating, and composed of metal particles dispersed in a continuous glassy matrix as a second phase, is disclosed, which permits good thermal conductivity, while retaining the electrical insulating character of the glass, thus providing improved packaging for electronic components.
Abstract: There is disclosed a composite body that is electrically insulating, and that is composed of metal particles dispersed in a continuous glassy matrix as a second phase. The metal particles are directionally anisotropic generally paralleling a predetermined plane through the body. This permits good thermal conductivity, while retaining the electrical insulating character of the glass, thus providing improved packaging for electronic components. A method of forming the composite body is also disclosed, as are methods of creating improved electronic packaging utilizing the composite material body.

9 citations


Journal ArticleDOI
01 Sep 1985
TL;DR: In this article, a three-course core for Electronic Packaging Engineering is described; this core can be used to provide electronic packaging engineering emphasis in the M.S. programs of a number of different departments.
Abstract: Characteristics of present and future problems and directions in Level 1 and Level 2 packaging are discussed. Research areas are delineated, and problems amenable to attack by universities are suggested. An example of an existing university research program is given. Methods for universities to develop and implement courses in electronic packaging are discussed. A three-course core presently in use is described; this core can be used to provide Electronic Packaging Engineering emphasis in the M.S. programs of a number of different departments. Guidelines are suggested for the development of educational programs in Electronic Packaging Engineering, including use of industrial interactions and video education.

6 citations


Proceedings ArticleDOI
29 May 1985
Abstract: An u l t r a -min ia tu re , gene ra l -pu rpose rub id ium gas ce l l f r equency s t anda rd has been des igned and i n v e s t i g a t e d e x p e r i m e n t a l l y , w i t h t h e aim of deve loping one of the smallest atomic frequency s t anda rds ye t deve loped . Th i s pape r desc r ibes t h e d e t a i l s o f t h e d e s i g n c o n c e p t and t h e e x p e r i mental results ob ta ined so f a r .

Proceedings ArticleDOI
01 Sep 1985

Journal ArticleDOI
TL;DR: In this paper, a set of customised high voltage integrated driving circuits was developed to meet the requirements of thin film electroluminescent display modules and hard competition in electronic display markets set boundaries for the setting of goals in the development of extremely thin display module.
Abstract: Demanding technical requirements of thin film electroluminescent display modules and hard competition in electronic display markets set boundaries for the setting of goals in the development of an extremely thin display module. To meet the targets the problems of electronic packaging concepts had to be considered from the point of view of total optimisation. As a result, a packaging concept was developed which had an influence on all design decisions starting from the end user's requirements and extending to the selection of a special semiconductor manufacturing process. A set of customised high voltage integrated driving circuits was developed. High density interconnection problems were solved by the tape automated bonding of semiconductors and a single‐sided two‐layer polymer thick film circuit board. Throughout the assembly process surface‐mounted components and reflow soldering methods were applied to form a large area printed polymer hybrid module. Viable volume production methods for a flat dot‐matrix display could be suggested.

Journal ArticleDOI
TL;DR: The characteristic impedance influences of superconducting packaging systems (in particular, Josephson packaging) on the degradation in transmitted signal rise time, amplitude distortions and crosstalk, signal propagation delay, and amplitude decay at the inductive and resistive connectors with matched capacitors are quantitatively evaluated by using the ASTAP computer simulation.
Abstract: The characteristic impedance influences of superconducting packaging systems (in particular, Josephson packaging) on the degradation in transmitted signal rise time, amplitude distortions and crosstalk, signal propagation delay, and amplitude decay at the inductive and resistive connectors with matched capacitors are quantitatively evaluated by using the ASTAP computer simulation. The present choice of the characteristic impedance Z/sub 0/ = 10- 12 Omega for a superconducting stripline is inadequate. Higher impedances of Z/sub 0/=40-50 Omega are useful from the standpoint of noise performance improvement. At the same time, a higher impedance choice can make the ground connector numbers of each connector decrease, which is preferable for a large-scale packaging system.

Journal ArticleDOI
James J. Farrell1
TL;DR: VLSI circuits challenge traditional electronic packaging methods, however, several new package types efficiently handle high-I/O devices.
Abstract: VLSI circuits challenge traditional electronic packaging methods. Several new package types, however, efficiently handle high-I/O devices.


Journal ArticleDOI
TL;DR: In this article, the focused output of a laser was used to write silver connections between device bonding pads and package conductors to fabricate a working clock, which was used in a novel device packaging scheme.
Abstract: A new method for forming low resistivity conductors in a doped polymer film has been used in a novel device packaging scheme. In a first application, the focused output of a laser is used to write silver connections between device bonding pads and package conductors to fabricate a working clock.

Journal ArticleDOI
TL;DR: In this paper, the tradeoff between product requirements and the characteristics of the packaging films available is discussed, and selection considerations are given for the application of specific materials of space hardware-related applications.
Abstract: Flexible packaging films are used to bag and/or wrap precision cleaned electronic or space hardware to protect them from environmental degradation during shipping and storage. Selection of packaging films depends on a knowledge of product requirements and packaging film characteristics. The literature presently available on protective packaging films has been updated to include new materials and to amplify space-related applications. Presently available packaging film materials are compared for their various characteristics: electrostatic discharge (ESD) control, flame retardancy, water vapor transmission rate, particulate shedding, molecular contamination, and transparency. The tradeoff between product requirements and the characteristics of the packaging films available are discussed. Selection considerations are given for the application of specific materials of space hardware-related applications. Applications for intimate, environmental, and electrostatic protective packaging are discussed.

Journal ArticleDOI
TL;DR: In this paper, the future trends of electronic interconnections to produce electronic equipment being manufactured in the Far East are discussed and details of simplistic circuits, as well as relatively complex multilayer boards used in new computer technology.
Abstract: This paper discusses the future trends of electronic interconnections to produce electronic equipment being manufactured in the Far East. Reviewed are details of simplistic circuits, as well as relatively complex multilayer boards used in new computer technology. The size of the market, techniques for component assembly, and various other aspects of the approach to electronic packaging are discussed.

Proceedings ArticleDOI
21 Oct 1985
TL;DR: In this article, the potential impact of new commercial/industrial packaging brief 1 y reviewed, and the problems encountered in implementing the most prominent of these, the leadless chip carrier, is detailed together with proposed solutions.
Abstract: Electronic packaging is in the midst of an international revolution. Higher device lead counts and potder dissipation accentuate system space, weight, testability, and cost constraints. While commercial /industrial electronics moves toward a new generation of sophisticated plastic encapsulated surface mounted devices, the military/ aerospace designer still has a more restricted set of choices. Device packages suitable for aerospace applications will be reviewed, and relative advantages and disadvantages described. Problems encountered in implementing the most prominent of these, the leadless chip carrier, will be detailed together with proposed solutions. National and international standardization activities will be discussed, and the potential impact of new commercial/industrial packaging brief 1 y reviewed.