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Showing papers on "Electronic packaging published in 1996"


Proceedings ArticleDOI
T.Y. Wu1, Y. Tsukada, W.T. Chen
28 May 1996
TL;DR: In this article, the authors present an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers, and how to apply this understanding in the modelling of design, process and reliability of flip chip.
Abstract: The strength of flip chip organic packaging technology rests upon the knowledge and manufacturing base of C4 solder bump chip interconnection, and printed circuit technology infrastructure. The key innovation was the underfill encapsulation between the chip and the laminate which overcame the road-block of low cycle fatigue of C4 solder bump due to large CTE difference between silicon and laminate. The advent of SLC (surface laminar circuit) innovation extends the flip chip technology to higher solder bump density and larger chip I/O expected for future generations of semiconductors. The flip chip packages contain new materials, interfaces, and new processes which in turn govern the mechanical integrity of the packaging module and module card assembly. The increasing pervasiveness of electronic packages requires meeting new sets of environments. It is important to have a good understanding of materials, interface, metrology and mechanics issues related to organic packages, and how to apply this understanding in the modelling of design, process and reliability of flip chip. This paper will deliver an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers.

120 citations


Patent
27 Nov 1996
TL;DR: In this article, an electronic packaging substrate which includes a sintered ceramic body having at least one internal layer of wiring and a cooling channel internal to and integral with the body for cooling a heat-generating electronic device was presented.
Abstract: Disclosed is an electronic packaging substrate which includes a sintered ceramic body having at least one internal layer of wiring and at least one cooling channel internal to and integral with the sintered ceramic body for cooling a heat-generating electronic device placed on the sintered body. Also disclosed is a method of making the electronic packaging substrate.

120 citations


Patent
16 Dec 1996
TL;DR: An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate as discussed by the authors.
Abstract: An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of semiconductor devices The input/output pads of the semiconductor devices are simultaneously bonded to the protuberances of the packaging module

119 citations


Patent
23 Apr 1996
TL;DR: In this article, a three-dimensional folded module has been proposed to reduce the overall footprint for interconnecting multiple semiconductor die by an approximate factor of four when compared to conventional electronic packaging.
Abstract: A three dimensional packaging approach reduces the overall footprint for interconnecting multiple semiconductor die. An three-dimensional folded module (10) produces a final package having a footprint size reduced by an approximate factor of four when compared to conventional electronic packaging. The module has a protective covering such as a cap (62) or a sealant (64) as a moisture barrier. Thus, high integration using flexible appendages (15, 25, 35, and 45) attached to a rigid substrate (12) and singularly folded above the substrate (12) results in both a small footprint package and also a light package. A reel-to-reel flex tape (56) assembly provides pre-tested flex boards (16, 26, 36, and 46) resulting in a cost-effective manufacturable package for semiconductor components.

99 citations


Journal ArticleDOI
01 May 1996-JOM
TL;DR: In this article, the authors compared the mechanical behavior of low-temperature materials (Sn-40In-20Pb, Sn-58Bi, and a silver-loaded conductive adhesive) and high-meltingtemperature solders (sn-3.5Ag, Sn 3.4Ag-4.8Bi, Sn 4.7 Ag-1.7Cu) to near-eutectic Sn-40Pb solder.
Abstract: A variety of new materials are needed for solder interconnects in electronic packages for high- and low-temperature applications. This article compares the mechanical behavior of low-temperature materials (Sn-40In-20Pb, Sn-58Bi, and a silver-loaded conductive adhesive) and high-melting-temperature solders (Sn-3.5Ag, Sn-3.4Ag-4.8Bi, and Sn-4.7 Ag-1.7Cu) to near-eutectic Sn-40Pb solder. The results indicate that there are promising materials alternatives to the traditional Sn-Pb solders in electronic interconnect applications.

92 citations


Journal ArticleDOI
Bongtae Han1, Yifan Guo1
TL;DR: Moire interferometry is proposed as a tool for the coefficient of thermal expansion (CTE) measurement of electronic packaging components as mentioned in this paper, which can produce the overall CTE and the local CTE across the entire component with high accuracy.
Abstract: Moire interferometry is proposed as a tool for the coefficient of thermal expansion (CTE) measurement of electronic packaging components. The method is a whole-field displacement measurement technique with a sub-micron sensitivity, which can produce the overall CTE and the local CTE across the entire component with high accuracy. The large dynamic range of the method makes it compatible with CTE evaluation of a broad range of components. Two experimental procedures are suggested for 1) CTE over a fixed temperature range and 2) CTE as a function of temperature. The procedures are implemented for various thin small outline packages (TSOPs) a plastic ball grid array (PBGA) package, and a stacked memory cube. The results emphasize the importance of a whole-field measurement technique. A supplementary thermo-mechanical analyzer (TMA) test on an aluminum alloy is conducted and the results are compared with a Moire measurement to discuss the accuracy of the proposed measurement procedure.

64 citations


Journal ArticleDOI
TL;DR: In this article, three optical methods with submicron sensitivities are employed: moire interferometry, microscopic moire Interferometry and Twyman/Green interferometers.
Abstract: Verified/predictive modeling has become an integral part of electronic packaging product development in order to reduce costs and cycle time. In this paper, interferometric displacement measurement methods are utilized to verify the validity of numerical models for microelectronics packaging design. Three optical methods with submicron sensitivities are employed: moire interferometry, microscopic moire interferometry and Twyman/Green interferometry. The first two provide contour maps of in-plane displacement fields, and the third maps out-of-plane displacement fields. Their high sensitivity and high spatial resolution make them ideally suited for verification of numerical models. By combining numerical modeling and experimental verification until the results merge, numerical models become more accurate and dependable. Then, the models can be applied extensively to optimize the package designs with confidence that the models provide effective information on material and geometry sensitivity.

56 citations


Proceedings ArticleDOI
28 May 1996
TL;DR: The Polymer Optical interconnect Technology (POINT) as mentioned in this paper is a collaborative program among GE, Honeywell, AMP, AlliedSignal, Columbia University and University of California at San Diego (UCSD) in developing affordable optoelectronic packaging and interconnect technologies for board-and backplane-level optical interconnect applications.
Abstract: The Polymer Optical interconnect Technology (POINT) is a collaborative program among GE, Honeywell, AMP, AlliedSignal, Columbia University and University of California at San Diego (UCSD), sponsored by ARPA, in developing affordable optoelectronic packaging and interconnect technologies for board- and backplane-level optical interconnect applications. The POINT program leverages on the existing electronic design, processing, fabrication and MCM packaging technologies to optoelectronic packaging. The POINT program also incorporates several state-of-the-art optoelectronic technologies that include: high speed VCSEL for multi-channel data transmission; flexible optical polymer waveguides and low-loss polymers for board and backplane interconnects; low-cost diffractive optical elements (DOE) for board-to-backplane interconnect; and use of molded MT-type connectors to reduce weight and size. In addition, to further reduce design and fabrication cycle times, CAD tools for multimode optical waveguide modelling, and for mechanical modelling of optoelectronic packaging will be employed to aid the technology development.

43 citations


Journal ArticleDOI
TL;DR: In this article, the authors simulate the partitioning of large silicon/complementary metaloxide-semiconductor (Si/CMOS) chips into tiled arrays of silicon chips, including in the analysis wiring lengths, electrical interconnect issues, I/O requirements, including drivers and electrostatic discharge (ESD) protection, wiring capacity, floorplans, wiring demand, escape, manufacturing yield, cost, and other electrical and thermal issues.
Abstract: Recent advances in area array chip bonding combined with the availability of high density substrates facilitate novel approaches to partitioning future systems. We examine one such new paradigm here: tiled silicon, in which system integration is achieved by tiling a set of chips together using area bonding on high density substrates rather than by pursuing single chip integration. We simulate the partitioning of large silicon/complementary metal-oxide-semiconductor (Si/CMOS) chips into tiled arrays of silicon chips, including in the analysis wiring lengths, electrical interconnect issues, I/O requirements, including drivers and electrostatic discharge (ESD) protection, wiring capacity, floorplans, wiring demand, escape, manufacturing yield, cost, and other electrical and thermal issues. Partitions are assumed to be interconnected via random logic, bus or memory type net topologies. Our results clearly show that it is possible to effectively tile silicon chips, when they are connected by reduced Rent exponent random logic, buses, or memory type net topologies. Systems with high interconnect demand, and thus little or no functional integration, cannot be tiled because of problems with larger chip real estate for drivers for off-chip lines and off-chip wiring capacity.

32 citations


Journal ArticleDOI
TL;DR: In this article, the authors used finite element analysis (FEA), design of experiments (DOE), and analytical techniques to determine the out-of-plane displacement of the corner leads of peripheral lead components when the local peripheral lead component/board assembly is subjected to bending moments in two directions.
Abstract: The rapid advancement of integrated circuits and associated electronic technologies have placed increasing demands on electronic packaging and its material structures in terms of the reliability requirements. In addition to the thermally induced stresses, electronic packages often experience dynamic external loads during shipping, handling, and/or operation. This is especially important for automotive, military, and commercial avionics operating environments. These dynamic loads give rise to large dynamic stresses in the leads causing fatigue failures. For peripheral leaded packages the corner leads are the most highly stressed leads. This paper addresses the determination of the out-of-plane displacement of the corner leads of peripheral leaded components when the local peripheral leaded component/board assembly is subjected to bending moments in two directions. The solution is achieved by using a combination of Finite Element Analysis (FEA), Design of Experiments (DOE), and analytical techniques. The out-of-plane displacement can then be applied as a boundary condition on a local lead model to determine the stresses which in turn can be used to estimate the fatigue life.

32 citations


Proceedings ArticleDOI
03 Feb 1996
TL;DR: In this article, the four basic three dimensional (3D) memory packaging technologies are described and a detailed discussion of how to apply 3D memory products are also discussed, considering design and test decisions on product cost.
Abstract: In response to the need for significant reductions in size and weight of digital electronic systems, several companies have developed packaging technologies that focus on miniaturization of memory functions. This paper describes the four basic three dimensional (3D) memory packaging technologies. Physical descriptions and sample photographs of the options provided. Metrics of packaging are developed to provide potential users a means of determining which technology might be best suited to their application. The basics of how to apply 3D memory products are also discussed. Consideration of design and test decisions on product cost are discussed. Also provided are examples of how 3D memory modules may be used in both processor multichip module (MCM) applications and in mass memory (solid-state recorder) applications.

Journal ArticleDOI
TL;DR: A new supply-demand framework for multiprocessor system design is proposed by considering packaging, processor, and interconnect technologies in an integrated manner and derives the best configuration while considering practical design aspects like maximum board area, maximum available pinout, fixed channel width, and scalability.
Abstract: Clustered or hierarchical interconnections have advantages when designing large scale multiprocessor systems. Earlier studies have either focused on only flat interconnections or proposed hierarchical/clustered interconnections with limited packaging and demanded performance constraints. Large systems require several levels of packaging. Packaging technologies impose various physical constraints on bisection bandwidth and channel width of a system. Pinout technologies and the capacity of packaging modules have been ignored in earlier studies, often leading to configurations that are not design-feasible. Similarly, the impact of processor and interconnect technologies on demanded performance has not been considered. We propose a new supply-demand framework for multiprocessor system design by considering packaging, processor, and interconnect technologies in an integrated manner. The elegance of this framework lies in its parameterised representation of different technologies. For a given set of technological parameters the framework derives the best configuration while considering practical design aspects like maximum board area, maximum available pinout, fixed channel width, and scalability. In order to build a scalable parallel system with a given number of processors, the framework explores the design space of flat k-ary n-cube topologies and their clustered variations (k-ary n-cube cluster-c) to derive design-feasible configurations with best system performance.

Proceedings ArticleDOI
03 Feb 1996
TL;DR: In this article, a 3D packaging concept is presented that supports three-dimensional (3D) interconnect of digital electronics using a stacked multichip module (MCM) approach, which offers an order of magnitude improvement in global communication bandwidth over traditional backplane techniques.
Abstract: A packaging concept is presented that supports three-dimensional (3-D) interconnect of digital electronics using a stacked multichip module (MCM) approach. The 3-D structure offers an order of magnitude improvement in global communication bandwidth over traditional backplane techniques. This is accomplished by simultaneously reducing interconnect length (propagation delay) and dramatically increasing physical connectivity between layers of electronics. A characterization cube is described that will demonstrate the key technologies behind the 3-D packaging concept. These include synthetic diamond substrates for heat conduction, spray cooling for heat removal, double-sided multi-layer MCM interconnect, and high density connectors that support the required inter-layer signal bandwidth. Size and weight benefits of 3-D packaging are quantified in a specific application comparison. Results suggest that machines normally confined to a computer room environment can be repackaged with this technology for airborne, shipborne, or mobile applications.

Journal ArticleDOI
S. J. Ham1, Soon-Bok Lee1
TL;DR: In this paper, an automated fatigue testing system was developed for an experimental study on the integrity of the electronic packaging subjected to mechanical vibration, which utilized the electromagnetic device as an actuator.
Abstract: An automated fatigue-testing system was developed for an experimental study on the integrity of the electronic packaging subjected to mechanical vibration. The fatigue-testing machine utilized the electromagnetic device as an actuator. A data acquisition system was developed for the fatigue test of the electronic board. The fixture for the specimen was designed to be suitable for measuring the fatigue life of a typical module/lead/card electronic system subjected to vibration. With this automated fatiguetesting machine, the mechanical integrity of surface mount component with the spider gullwing leads has been studied by a mechanical flexural fatigue test. An experimental method was developed to measure the changes in electrical resistance in the lead, which is used to indicate a fatigue failure. Finally, a relationship between the loading force and the fatigue life of high-cycle region was discussed for the lead of spider gullwing type surface-mounted component. With the relation, the fatigue life of the surface-mounted component (SMC) subjected to vibration environment was predicted successfully.

Patent
25 Oct 1996
TL;DR: An assembly support mount as discussed by the authors includes at least two flexible, retention posts spaced apart with ends to engage a heat sink frictionally to support the heat sink relative to an electronic device, where the flexible posts are attached to a substrate without the need for holes in the substrate and extend past a heat generating device into openings in a heat sinks where they are attached by any number of means, preferrably by frictionally engaging the openings in the heat sinks.
Abstract: An assembly support mount includes at least two flexible, retention posts spaced apart with ends to engage a heat sink frictionally to support the heat sink relative to an electronic device. The flexible retention posts are attached to a substrate without the need for holes in the substrate and extend past a heat generating device into openings in a heat sink where they are attached by any number of means, preferrably by frictionally engaging the openings in the heat sink.

Journal ArticleDOI
TL;DR: In this article, the authors present the reliability test results of flip-chip interconnection technology using conductive adhesive joining and present the electrical contact nature of the adhesive joint in the light of continuous and static electrical resistance measurement.
Abstract: Electronic packaging is increasingly becoming a vital part of the electronics industry, representing a key barrier to cost reduction and performance improvement. Of all the packaging methods, flip‐chip technology offers, up to now, the highest packaging density and best electrical performance. In this paper, flip‐chip test design considerations, process development and driving forces for adhesive joining and soldering flip‐chip processes will be given. Reliability test results of flip‐chip interconnection technology using conductive adhesive joining will also be presented. The electrical contact nature of the adhesive joint will be elaborated in the light of continuous and static electrical resistance measurement. Future research work directions in flip‐chip joining using eutectic solder and conductive adhesives on flexible circuits will also be discussed.

Journal ArticleDOI
TL;DR: In this paper, the suitability of a combined experimental and computational methodology for system-level electronic packaging thermal design was examined and the best configuration based on model study was experimentally examined and provided maximum surface temperature reduction of 56%.
Abstract: The present study examines the suitability of a combined experimental and computational methodology for system-level electronic packaging thermal design. A 48.3 cm (19 in), twenty-slot, fully populated commercial-off-the-shelf (COTS) electronic equipment chassis was studied experimentally and computationally. The experimental program involved detailed component surface temperature measurements for system power levels of 423 and 846 W (21 and 42 W/module) and for volumetric flow rates between 0.05 and 0.14 m/sup 3//s. The experimental configuration was also computationally simulated and the predicted component temperatures agreed well with the experiments. The effects of various baffle configuration designs within the inlet plenum were then computationally analyzed for improved thermal performance. The best configuration based on the model study was experimentally examined and provided maximum surface temperature reduction of 56%.

Journal ArticleDOI
TL;DR: An overview of the concerns involved in the operation of electronic hardware at elevated temperatures is presented in this paper, where materials selection and package design issues are addressed for a wide range of packaging elements from the semiconductor chip to the box.
Abstract: An overview of the concerns involved in the operation of electronic hardware at elevated temperatures is presented. Materials selection and package design issues are addressed for a wide range of packaging elements from the semiconductor chip to the box. It is found that most elements of common high density device and packaging architecture can be used up to 200°C. However, gold‐aluminium wirebonds, eutectic tin‐lead solder joints and die attaches, and FR‐4 boards will seriously degrade at temperatures below 200°C. For these elements, alternative materials of construction are recommended. Comparisons are made between package design for high power dissipation and that for high temperature operation.

Journal ArticleDOI
TL;DR: In this article, the authors present new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 µm pitch area array component using anisotropic conductive adhesive (ACA) materials.
Abstract: This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 /spl mu/m pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (/spl mu/BGA), chip scale packaging (CSP), and also flip-chip and conventional ball grid array (BGA) package structures. A range of materials combinations have been evaluated, including (random filled) adhesive materials based on both thermoplastic and thermosetting resin systems, combined with both organic and thick-film on ceramic substrate materials. The ACAs used have all been applied as films, and hence are also known as anisotropic conducting films (ACF). The test assemblies have been constructed using a specially developed instrumented assembly system which allows the measurement of the process temperatures and pressures and the consequent bondline thickness reduction and conductivity development. The effects of the process parameters on the resulting properties, particularly conductivity and yield, are reported, A complementary paper indicates the results of computational fluid dynamics (CFD) models of the early stages of the assembly process which allow the extrapolation of the present results to finer pitch geometries.

Journal ArticleDOI
TL;DR: In this article, the authors discuss electrochemical migration in general, and conductive filament formation in particular, and its impact on the reliability of multichip modules (MCM•L).
Abstract: Laminated substrates are used widely in the manufacture of multichip modules (MCM‐L) by the electronic packaging industry. Of late, the thrust has been towards higher density circuitry to achieve improved performance and reduced size. This has led to the use of finer lines and spacings, smaller drilled holes and buried vias in organic laminates leading to reliability issues such as electrochemical migration. One of the forms of electrochemical migration is known as conductive filament formation. Conductive filament formation is an electrochemical process. In accelerated environments of temperature and humidity, organic laminates can develop a loss of insulation resistance between conductors, eventually resulting in loss of electrical function of the circuit. The paper aims at discussing electrochemical migration in general, and conductive filament formation in particular, and its impact on the reliability of MCM‐L.

Proceedings ArticleDOI
28 May 1996
TL;DR: A semi-implicit time integration scheme for a cyclic thermoviscoplastic constitutive model with tensorial internal state variables for Pb-Sn solder, a common metallic constituent in electronic packaging applications, was developed in this article.
Abstract: A semi-implicit time integration scheme has been developed for a cyclic thermoviscoplastic constitutive model with tensorial internal state variables for Pb-Sn solder, a common metallic constituent in electronic packaging applications. The procedure has been implemented numerically into the commercial finite element (FE) code ABAQUS (1995) by user-defined material subroutines. Several simulations are conducted to compare the numerical implementation to experiments including monotonic uniaxial tests at different temperatures, creep tests at four stress levels, and a test with two-step load-controlled cyclic loading for 62Sn36Pb2Ag solder. An explicit time integration scheme is used as well to compare with the semi-implicit scheme. The accuracy as well as the stability of the solutions are considered. Several suggestions are made for using the material constitutive model and the semi-implicit integration scheme for modeling solder connections. This work provides guidelines to implement user-defined material behavior into FE analyses to perform more sophisticated thermomechanical simulations for solder connections in electronic packaging applications.

Proceedings ArticleDOI
28 May 1996
TL;DR: The Plastic Packaging Consortium (PPC) as mentioned in this paper was a funded Technology Reinvestment Project (TRP) awarded in the FY94 competition on low-cost electronic packaging, which focused on three areas of improvement: (1) plastic package "ruggedization", (2) PL thermal enhancement, and (3) high density plastic packages.
Abstract: The Plastic Packaging Consortium is a funded Technology Reinvestment Project (TRP) awarded in the FY94 competition on low-cost electronic packaging. The ten companies $20M+ cost-shared effort, led by National Semiconductor Corp., will establish the on-shore infrastructure to manufacture low-cost, high density, high performance "ruggedized" plastic packages. This initiative comes from the increasing need to improve complexity, performance, and reliability of plastic packages for both military and commercial use, while lowering the total system cost. The Program focuses on three areas of improvement: (1) plastic package "ruggedization"; (2) plastic package thermal enhancement; and, (3) high density plastic packages. Advances in molding compounds, die attach materials, leadframe materials, leadframe design, and reliability characterization will be accomplished. The deliverables at the end of the two-year Program will be plastic package processes and materials, which require no dry-bagging, eliminate "popcorning", improve low-cost (stamped) fine pitch leadframes, and utilize low-cost interconnect processes for high density packaging. This paper reports the results obtained in the three focus areas after the first year of activities.

Patent
31 Jul 1996
TL;DR: In this paper, a method for adherently bonding metal-diamond bonding was proposed to yield high thermal conductivity and dielectric isolation, while being compatible with electronic package fabrication and attachment of most semiconductor devices.
Abstract: The present invention pertains to the packaging of electronic circuit. More particularly, the present invention pertains to methods for adherently bonding metals (4) to diamond (1) (i.e. the formation of a metal-diamond bonded structure) to yield metal-diamond substrates which are suitable for use in the fabrication of electronic packaging. These metal-diamond substrates exhibit both high thermal conductivity and dielectric isolation (where necessary), while being compatible with electronic package fabrication and the attachment of most semiconductor devices. The methods of the present invention include the formation of adherently bonded metal (5) by: the metallization of a bare diamond surface by the deposition of base coat or primer coat comprising certain carbide-forming metals such as molybdenum and tungsten; the metalization of a bare diamond surface using an active braze alloy; and by the growth of a diamond layer on a carbide-forming substrate by chemical vapor deposition (CVD).

Journal ArticleDOI
28 May 1996
TL;DR: The experiments completed demonstrate that parallel optics can dramatically increase the capacity of telecommunications equipment with no significant changes in system or physical architecture.
Abstract: Optoelectronic modules and multifiber optical connectors were successfully applied to intrasystem interconnection within a large telecommunication transmission terminal. The optoelectronic modules are 32-channel 850 nm vertical cavity surface emitting laser (VCSEL) and detector arrays packaged using multichip module technology system components include multimode silica optical fibers and silicon V-groove technology based multifiber optical connectors. The system architecture presented particularly difficult challenges for parallel optics because of complex cable assemblies required by the fan-out nature of the cables and the signal bifurcation needed to accomplish duplication, Nevertheless, the experiments completed demonstrate that parallel optics can dramatically increase the capacity of telecommunications equipment with no significant changes in system or physical architecture. The density of the optical modules and connectors clearly demonstrates that optical interconnection technology will be able to support the input/output (I/O) requirements of new generations of integrated circuit technology.

Journal ArticleDOI
TL;DR: The Packaging Revolution of the ’90s, powered by the perpetual drive for smaller-faster-cheaper products, is placing increasing demands on the electronic materials sector.
Abstract: The Packaging Revolution of the ’90s, powered by the perpetual drive for smaller‐faster‐cheaper products, is placing increasing demands on the electronic materials sector. Down‐sizing, without a cost penalty, requires new materials and processes. Electronic polymers are playing an increasingly vital role as area array, chip size components and packageless designs become mainstream technologies. Micro‐Ball Grid Arrays (micro‐BGA), Chip Scale Packages (CSP) and Chip‐on‐Board(COB) require new adhesives and encapsulants that enable the use of low‐cost, high density organic‐based wiring and interconnect structures. Concurrently, new, simplified processes are being developed in order to streamline high volume manufacturing. This paper discusses quick bonding film die attach adhesives, fast‐flow flip‐chip underfills, and a variety of liquid encapsulants as well as new conductive adhesives designed for flip‐chip and micro‐Package assembly. Process innovations include the new Printed Package concept and the appeal...

Journal ArticleDOI
TL;DR: In this paper, the authors used scanning acoustic microscopy (SAM) for determining the quality and reliability of chip on-board (COB) and Flip Chip adhered devices.

Journal ArticleDOI
TL;DR: Flexible circuits are ideally suited to solving the design demands of next generation electronics as mentioned in this paper and offer a number of advantages that are unavailable to those using more traditional, rigid type interconnection structures.
Abstract: Flexible circuits are ideally suited to solving the design demands of next generation electronics The flexible circuit offers a number of advantages that are unavailable to those using more traditional, rigid type interconnection structures A number of new applications for flexible circuits have been developed that may well provide a glimpse of what is yet to come in electronic packaging technology These new applications embrace the whole spectrum of the electronics interconnection world from chip packaging to high density multilayer structures Reviewed here are some of the more novel uses of the flex circuit for high performance electronic interconnection

Proceedings ArticleDOI
T.C. Chung1, F. Ghahghahi, B. Oberlin, D. Carey, D. Nelson 
28 May 1996
TL;DR: This paper discusses AAP-related developmental findings, especially in the areas of ball grid arrays, direct chip attach (DCA), and multichip module-laminate (MCM-L) related technologies, including packaging requirements; a trade-off study of a 300 MHz computer workstation.
Abstract: Tandem Computers Incorporated has been working with the Microelectronics and Computer Technology Corporation (MCC), along with its member companies, to actively develop area array packaging (AAP) related technologies for next-generation workstation/multiprocessor module packaging. Since 1990, Tandem has participated in several MCC projects, such as the Open Systems Project (OSP1), its follow-on (OSP2), and the Packaging for Parallel Processing (PPP) Project. In this paper, we discuss our AAP-related developmental findings, especially in the areas of ball grid arrays (BGAs), direct chip attach (DCA), and multichip module-laminate (MCM-L) related technologies, including packaging requirements; a trade-off study of a 300 MHz computer workstation; large, high-I/O BGA (up to 44 mm square, with 1089 I/Os) and DCA (up to 20 mm square, with /spl sim/2200 I/Os) technology developments; advanced MCM-L substrate technology; escape routing for AAP; BGA and DCA assembly technologies; characteristics of flip chip underfill performance; reliability modeling and testing results; and electrical signal integrity.

Journal ArticleDOI
TL;DR: In this article, the use of an emerging process technique for curing of polymer encapsulants as used in the electronic packaging industry has been reported, which has demonstrated the usefulness of sweeping operating frequencies in order to achieve high levels of electric field uniformity and process control.
Abstract: This paper reports on the use of an emerging process technique for curing of polymer encapsulants as used in the electronic packaging industry. Previous work performed in the area of materials processing has demonstrated the usefulness of sweeping operating frequencies in order to achieve high levels of electric field uniformity and process control. The use of controlled variable frequency microwave energy has been evaluated as a process technique compatible with electronic packaging requirements. The heating of a series of integrated circuits (ICs) and their subsequent characterization was performed. IC integrity was investigated using X-Ray, Acoustic Microscopy, Decapsulation and Bond Pull. Processing of liquid encapsulants, underfills and glob-tops, used in Flip Chip and Chip On Board (COB) applications, was performed. Differential Scanning Calorimetry was used to study cure extent. Further studies show that variable frequency microwave processing leads to fast curing of encapsulants. A reduction in cycle times from 15 to 20 times over conventional curing has been observed. Also, results have showed a reduction in the stresses induced by mismatches in coefficient of thermal expansion.

Proceedings ArticleDOI
18 Oct 1996
TL;DR: The NEAR laser range finder (NLR) as mentioned in this paper is a compact, light weight design with a high power laser transmitter and a high performance mirror receiver system, which provides the in-situ distance measurement from the spacecraft to a near earth asteroid.
Abstract: The NEAR laser range finder (NLR) design is a compact, light weight design with a high power laser transmitter and a high performance mirror receiver system. One of the main objectives of the NLR is to provide the in-situ distance measurement from the spacecraft to a near earth asteroid. An on board computer will compile this information to provide necessary navigation requirements for the NEAR satellite. Due to the weight budget constraint, the maximum weight limitation of the NLR has been a critical issue from the beginning of the program. To achieve this goal and meet the system design objectives, innovative designs have been implemented in the development of light weight optical, mechanism, and electronic packaging hardware. This paper provides details of the NLR electronic packaging design, thermal and structural designs.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.