Showing papers on "Electronic packaging published in 1999"

Challenges in the packaging of MEMS

Abstract: Unlike IC packaging, MEMS dice must interface with the environment for sensing, interconnection, and/or actuation. MEMS packaging is application specific and the package provides the physical interface of the MEMS device to the environment. In the case of a fluid mass flow control sensor, the medium flows into and out of the package. This type of packaging is referred to as media compatible packaging. Harsh environments may create different challenges for the packaging of MEMS. In addition to challenges related to the MEMS chip environment and interfacing with that environment, challenges also exist inside the MEMS package, such as die handling, die attach, interfacial stress, and outgassing. These new challenges in MEMS packaging need immediate research and development efforts. To date, most of what is known about MEMS packaging remain proprietary secrets and published literature is scarce. The challenges of MEMS packaging have been known for some time, but little open research has been done to collect data and work toward meeting these challenges. A disproportionality exists between money spent on MEMS packaging and time spent researching MEMS packaging. Currently, the cost of MEMS packaging typically accounts for 75% or more of the device sale price. MEMS packaging is already far behind the capabilities of MEMS designers, and it is the purpose of this paper to share the challenges of MEMS packaging and create an awareness and an interest in MEMS packaging within the packaging community.

The Electronic Packaging Handbook

Abstract: The packaging of electronic devices and systems represents a significant challenge for product designers and managers. Performance, efficiency, cost considerations, dealing with the newer IC packaging technologies, and EMI/RFI issues all come into play. Thermal considerations at both the device and the systems level are also necessary.The Electronic Packaging Handbook, a new volume in the Electrical Engineering Handbook Series, provides essential factual information on the design, manufacturing, and testing of electronic devices and systems.Co-published with the IEEE, this is an ideal resource for engineers and technicians involved in any aspect of design, production, testing or packaging of electronic products, regardless of whether they are commercial or industrial in nature. Topics addressed include design automation, new IC packaging technologies, materials, testing, and safety.Electronics packaging continues to include expanding and evolving topics and technologies, as the demand for smaller, faster, and lighter products continues without signs of abatement. These demands mean that individuals in each of the specialty areas involved in electronics packaging-such as electronic, mechanical, and thermal designers, and manufacturing and test engineers-are all interdependent on each others knowledge. The Electronic Packaging Handbook elucidates these specialty areas and helps individuals broaden their knowledge base in this ever-growing field.

An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures

Abstract: Power electronics building blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At the Center for Power Electronics Systems, we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double what could be achieved with commercially packaged devices of the same rating.

Power electronic module packaging

Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.

Conjugated and Fullerene-Containing Polymers for Electronic and Photonic Applications: Advanced Syntheses and Microlithographic Fabrications

Abstract: Polymers have traditionally been used for so-called passive applications in many areas of electronics, for instance, as passivation and insulating materials in electronic packaging and as lithograp...

Comparative study of thermally conductive fillers for use in liquid encapsulants for electronic packaging

Abstract: Thermal management plays a very vital role in the packaging of high performance electronic devices. Effective heat dissipation is crucial to enhance the performance and reliability of the packaged devices. Liquid encapsulants used for glob top, potting, and underfilling applications can strongly influence the package heat dissipation. Unlike molding compounds, the filler loading in these encapsulants is restrained. This paper deals with the development and characterization of thermally conductive encapsulants with relatively low filler loading. A comparative study on the effect of different ceramic fillers on the thermal conductivity and other critical properties of an epoxy based liquid encapsulant is presented.

Thermal impact of solder voids in the electronic packaging of power devices

Abstract: The subject of this paper is the thermal impact of solder voids in the electronic packaging of semiconductor power devices. First, the pros and cons of some conventional methods used in thermal analysis are assessed, with emphasis on the accuracy of the commonly-used 45/spl deg/ model in calculating thermal resistance. Finite element thermal analysis is then applied to the case of different solder voids, which are classified and modeled numerically. The thermal resistance for each case is calculated and compared. It is found that different kinds of solder voids have a quite different impact upon the overall package thermal impedance. Large, coalesced voids have a more significant effect than small, distributed voids. The influence of solder voids on the example of a semiconductor laser chip is also analyzed. It is found that the long strip-type heat generating areas/volumes associated with semiconductor laser chips result in a strong sensitivity to the orientation of solder voids underneath. Finally, solder joint inspection criteria outlined in MIL-STD-883D method 2030 are discussed. Some possible modifications are proposed for the inspection of solder joints in semiconductor laser chip bonding.

Materials issues in area-array microelectronic packaging

Abstract: The important issues in advanced area-array electronic packaging for semiconductor devices are materials driven. Some of the processing-driven materials issues include the effect of introducing a silicon device interface with copper pads and a low-κ dielectric, the effect of decreasing pitch and feature size on the package interconnects, the development and implementation of organic substrates, and advanced underfills for fine-pitch flip-chip applications. From a materials reliability aspect, important materials issues include enhanced solder interconnect reliability, α-particle-induced soft errors, and the introduction of lead-free solder alloys.

Method and structure of z-connected laminated substrate for high density electronic packaging

Abstract: Structures, methods and materials for making multilayer circuit substrates are disclosed. The structures include bumped structures or microencapsulated conductive particles suitable for use in a lamination process to make a multilayer printed circuit substrate.

Electronic packaging device and method

Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a plurality of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the wire leads of the component routed through the lead channels. A plurality of lead terminals, adapted to cooperate with the specially shaped lead channels, are received within the lead channels, thereby forming an electrical connection between the lead terminals and the wire leads of the electronic component(s). The special shaping of the lead channels and lead terminals restricts the movement of the lead terminals within the lead channels in multiple directions during package fabrication, thereby allowing for the manufacture of larger, more reliable devices. In another aspect of the invention, the device includes a series of specially shaped through-holes are provided within the base member to allow the routing of wire leads there through. The bottom surface of the base member is chamfered to facilitate “wicking” of molten solder up the wire leads during soldering, thereby allowing for a stronger and more reliable joint. A method of fabricating the device is also disclosed.

Thermal management for multifunctional structures

Abstract: Multifunctional structures (MFS) are an innovative concept that offer a new methodology for spacecraft design, eliminating chassis, cables and connectors, and integrating the electronics into the walls of the spacecraft. The MFS design consists of multilayer flexible circuit patches bonded onto a structural composite panel, and multichip modules (MCMs) performing specific functions are bonded onto the circuit patches which are interconnected via flexible circuit jumpers. Incorporation of the high power density two-dimensional (2-D) and three-dimensional (3-D) MCM's into smaller and more efficient packaging designs still has the fundamental requirement to maintain component temperatures within design limits. Higher component qualification temperatures, such as 393 K, can result in smaller spacecraft radiator areas that are consistent with efficient packaging schemes. During the MFS development effort, a structural radiator panel was fabricated using high thermal conductivity (Hi-K) composite facesheets, and several thermal management designs using combinations of Hi-K doublers (150-1500 W/m-K), Hi-K (150-700 W/m-K) corefill, and deployable radiators to maximize MCM's heat rejection. Results of the thermal vacuum tests and details of the thermal design methodology are presented in this paper.

Board-level characterization of 1.0 and 1.27 mm pitch PBGA for automotive under-hood applications

Abstract: Ball grid array (BGA) has become the mainstream package of choice for devices with pin counts greater than 160. As such, the current generation of automotive engine and electronic transmission controllers for under-hood and on-engine mounting with pin counts in the 200 to 350 pin count range are being introduced by Motorola in BGA packaging. There is also a driving force to reduce the form factor of automotive electronics, both due to space constraints and to achieve lower material costs. All this is occurring while there is a shift to put more electronics under-hood and specifically on-engine, where temperatures can be greater than typical firewall mounting. One special concern with the BGA, therefore, is its ability to withstand the repeated cycling associated with these applications up to temperatures that can approach 150/spl deg/C. This paper will outline testing and simulation using finite element analysis (FEA) that was performed to assess the board-level (i.e., package to board interconnect) reliability of both 1.0 and 1.27 mm pitch PBGAs for the severe automotive environment. Variables such as package body size, die size, ball size, package substrate thickness, solder ball pitch and the presence/absence of thermal balls will be addressed. Solder joint fatigue failure data from the commonly used -40 to 125/spl deg/C automotive thermal cycling condition as well a more severe potentially required condition of -50 to 150/spl deg/C will be presented to show the suitability of PBGA for the intended application from a solder joint reliability perspective.

Package for electronic devices

Abstract: An electronic packaging module for bonding of power semiconductor devices is produced. The semiconductor device is mounted on a base, and enclosed by a frame and lid. The lid is an insulating substrate having a conductive pattern with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the metallization pads of semiconductor devices. The metal protuberances are bonded to the semiconductor device joining it to the lid, and through the conductive pattern of the lid connecting the device to the input/output contacts of the package.

Ultra-thin electronic device package

Abstract: We report in this article a feasibility study of ultra-thin device packages that combine thin IC chips, thin flex circuit and adhesive flip chip technology. Using this novel packaging concept, we constructed a 512 Kbyte SRAM memory module that was less than 150 micron thick. Even more profoundly, the package was flexible enough to conform to nonplanar surfaces. This unique property can lead to new applications that would not be feasible otherwise and extend the reach of electronics into brand new areas. Two of these ultra-thin modules were stacked to construct a 3D package with 1 Mbyte of memory capacity that is /spl sim/30 times thinner and 30 times lighter than a conventionally packaged device.

Electronic packaging and method of packaging

Abstract: Protective packaging for electronic equipment includes an expanded foam body with cavities for components, air ducts, and the like. An outer EMI bag surrounds the equipment containing foam body. The assembly is enclosed within a deformable exterior case which includes front and rear covers, air filters, or fans. The cases are modular and stackable. Integrally formed connectors electrically couple adjacent cases together. The connectors couple the EMI bags together to form a common shield.

Adhesion issues in flip-chip on organic modules

Abstract: Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses.

Optomechanical design and characterization of a printed-circuit-board-based free-space optical interconnect package

Abstract: We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI's) can be integrated simply on electronic multichip modules (MCM's) for intra-MCM-board interconnects. Our system-level packaging architecture is based on a modified folded 4f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than -20 dB at low frequency have been measured. The system is compact at only 10 in.3 (25.4 cm3) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Design of Passive Components for K-Band Communication Modules in LTCC Environment

Abstract: The ongoing development of LTCC materials and multilayer processes are making this technology more and more attractive for use in the manufacture of microwave multichip modules. However, prior to the manufacture of modules, the high frequency behavior of the passive RF components needs to be investigated to determine the performance limitations due to the manufacturing process. The aim of this paper is to give solutions for waveguides and transitions that can be applied in the packaging of a 24 GHz communication link module. The passive components have been designed with the assistance of 3D electromagnetic field simulations using a Finite Difference Time Domain technique. Several types of transitions from the top of the LTCC to an inner layer and back to the top, which are used for the feeding of hermetic sealed packages, are considered. These activities are supported by the European community through the Brite-Euram project RAMP 1

UBM Formation on Single Die/Dice for Flip Chip Applications

Abstract: Flip Chip bonding is well known to have many advantages and it has been used for many applications in the electronic packaging industry to achieve high I/O count and high electrical performance. Currently, Under Bump Metallurgy (UBM) is one of the most important methodologies to obtain reliable connections in the solder bump structure of the Flip Chip. UBM can be deposited on wafers through various techniques such as sputtering, evaporation, or electroless plating. However, these processes are only suitable for very high volume production, but in general, they are not practical for use in prototyping stages or in low volume production, especially where the entire wafer is not readily accessible. This paper reports a low cost UBM deposition process for use on a single die or a number of dice. This new technique will allow Flip Chip bonding to be based on a single die and will be suitable for low volume applications. The UBM deposition process on aluminum pads of a single die consists of two major processing steps. Firstly, step one temporarily attaches the die to a substrate using an amorphous thermoplastic adhesive. Such adhesives may be cleanly removed from the die backside, with suitable solvents, after the UBM deposition is achieved. The second step is to deposit the UBM layer using nickel electroless plating. A zincation process is performed to pretreat the aluminum surface prior to the plating process. This paper will discuss in details the procedures used in each process step as well as the experimental results and the analysis of data for the newly developed process.

Packaging for a 40-channel parallel optical interconnection module with an over-25-Gbit/s throughput

Abstract: NTT is currently working on developing a high-throughput interconnection module that is both compact and cost effective. The technology being developed is called "parallel inter-board optical interconnection technology", or "ParaBIT". The ParaBIT module that has been developed is the first step; it is a front-end module with 40 channels, a throughput of over 25 Gbit/s, and a transmission distance of over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays enable the same packaging structure to be used for both the transmitter and receiver. To achieve super-multichannel performance, high-density multiport bare-fiber (BF) connectors were developed for the module's optical interface. Unlike conventional optical connectors, these BF connectors do not need a ferrule or spring. This ensures physical contact with an excellent insertion loss (less than 0.1 dB per channel). A polymeric optical waveguide film with a 45/spl deg/ mirror for coupling to the VCSEL and photo-diode (PD) arrays by passive optical alignment was also developed. To facilitate coupling between the VCSEL/PD array chips and the waveguide, a packaging technique was developed to align and die bond the optical array chips on a substrate. This technique is called transferred multichip bonding (TMB); it can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques enabled ultra-parallel interconnections to be achieved in prototype ParaBIT modules.

Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition

Abstract: The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.

High reliability, high density, low cost packaging systems for matrix systems for matrix BGA and CSP by vacuum printing encapsulation systems (VPES)

Abstract: Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology.

Modular electronics packaging system

Abstract: A modular electronics packaging system includes multiple packaging slices that are mounted horizontally to a base structure. The slices interlock to provide added structural support. Each packaging slice includes a rigid and thermally conductive housing having four side walls that together form a cavity to house an electronic circuit. The chamber is enclosed on one end by an end wall, or web, that isolates the electronic circuit from a circuit in an adjacent packaging slice. The web also provides a thermal path between the electronic circuit and the base structure. Each slice also includes a mounting bracket that connects the packaging slice to the base structure. Four guide pins protrude from the slice into four corresponding receptacles in an adjacent slice. A locking element, such as a set screw, protrudes into each receptacle and interlocks with the corresponding guide pin. A conduit is formed in the slice to allow electrical connection to the electronic circuit.

Packaging technologies for RFICs: current status and future trends

Abstract: In the current wireless market, competitive pressures are driving the electrical performance of RF integrated circuit (RFIC) devices to new levels. At the same time, the demands placed on packaging of these RFICs have caused more resources to be focused on solutions. The result has been that high frequency packaging is called upon to provide low cost, thermally efficient, miniaturized products for a wide range of wireless telecommunications applications. The packaging of RFICs covers a wide range of technologies, with a number showing promise for future developments. The end applications for these packaged devices range from fixed base systems to high portability, handheld uses. Both types require that aggressive performance and economic consideration be paid to packaging technique. The dominant package options are the single chip plastic encapsulated RFIC and its cousin, the ceramic package. Advanced package technologies include the many forms of multiple chip modules (MCM), leadless array packaging (including ball grid array (BGA) and near-chip scale pages), as well as thermally enhanced packaging in ceramic and laminate substrate materials. In looking ahead to the next generations of packages, a key determinant lies on the road to advanced packaging for RFICs. System level integration and manufacturing technology for wireless products will likely remain primarily surface mount technology (SMT). With this constraint; smaller, higher levels of device integration, increased thermal capability and integration will place increased burdens on packaging technology. Some insights into potential emerging technologies and their enabling requirements will be offered.

Cost-effective manufacturing of aluminium silicon carbide (AlSiC) electronic packages

Abstract: Current microelectronics places ever increasing demands on the performance of electronic packaging materials and systems in terms of thermal management, weight, and functionality requirements. These requirements have pushed the development of new materials and processing technologies to provide high performance packaging solutions cost-effectively. Aluminum silicon carbide (AlSiC) metal matrix composite (MMC) packages have a unique set of material properties that are ideally suited to the above requirements. The AlSiC coefficient of thermal expansion (CTE) value is compatible with direct IC device attachment, allowing for the maximum thermal dissipation into the high thermal conductivity (170-200 W/mK) AlSiC package. Additionally, the low material density of AlSiC (3 g/cm/sup 3/) makes it ideal for weight sensitive applications. The Ceramics Process Systems (CPS) AlSiC fabrication and processing technology provides both the material and the net-shape functional packaging geometry in one process step. This processing technology also allows the Concurrent Integration/sup TM/ of feedthroughs, seal rings and substrates, which eliminates the need for additional assembly operations. These manufacturing attributes allow AlSiC packaging to be cost competitive and offer performance advantages over competing packaging products/systems. The AlSiC packaging design process and manufacturing process is outlined through actual product examples.

Fluid delivery systems for electronic device manufacture

Abstract: The present invention relates to new methods for delivering solutions during electronic device manufacture. Methods of the invention include delivering metallization solutions to the device at an angle of less than 90 degrees with the surface of the device. The method may further comprise partially treating the device by delivering the metallization solutions from above the device, turning the device over, and then completing treatment by delivering the metallization solutions from below the article. The method is particularly useful in the formation of printed circuit boards and other electronic packaging devices having through-holes and blind vias.

Electrical evaluation of flip-chip package alternatives for next generation microprocessors

Abstract: Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages.