Showing papers on "Electronic packaging published in 2004"

SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade

Abstract: In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.

Glass frit bonding : An universal technology for wafer level encapsulation and packaging

Abstract: This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass-frit bonding.

Design of compact stacked-patch antennas in LTCC multilayer packaging modules for wireless applications

Abstract: A simple procedure for the design of compact stacked-patch antennas is presented based on LTCC multilayer packaging technology. The advantage of this topology is that only one parameter, i.e., the substrate thickness (or equivalently the number of LTCC layers), needs to be adjusted in order to achieve an optimized bandwidth performance. The validity of the new design strategy is verified through applying it to practical compact antenna design for several wireless communication bands, including ISM 2.4-GHz band, IEEE 802.11a 5.8-GHz, and LMDS 28-GHz band. It is shown that a 10-dB return-loss bandwidth of 7% can be achieved for the LTCC (/spl epsiv//sub r/=5.6) multilayer structure with a thickness of less than 0.03 wavelengths, which can be realized using a different number of laminated layers for different frequencies (e.g., three layers for the 28-GHz band).

Chip scale thermal management of high brightness LED packages

Abstract: The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of lo calized hot spots at the chip active layer. The importance of “zero defects” in one of the more popular interconnect schemes; the “epi down” soldered flip chip configuration is investigated and demonstrated. Keywords: High brightness LEDs, Infrared imaging, Microscopic IR, Bump defects, Finite element analysis.

3D packaging: where all technologies come together

Abstract: Cell phones and consumer products like digital cameras, PDAs and other wireless devices require maximum functional integration in the smallest footprint, lowest profile and low cost package. CSPs have minimized the footprint to achieve a chip/package area ratio about 80%. 3D packaging has increased that ratio to the impressive level of > 200% without increasing the thickness or the footprint of the package. Integration in the z-direction is achieved by stacking die or stacking packages and interconnecting them with wire bonding. 3D packages are assembled using the established packaging infrastructure and supply chain which offers design flexibility, short time-to-market, low risk and low cost product introduction. 3D packaging poses two challenges. First, the stacking of more chips in a thinner package stretches the performance envelope of all assembly process, materials and equipment. Narrower process margins, thin layer materials, equipment with higher precision and flexibility require trade-offs to minimize risk and cost without compromising the reliability of the package. Second, the testing of the final module requires that package design allow access to all the chips. Integration of complex chips from multiple suppliers in one package creates a high value module and increased test complexity.

System design issues for 3D system-in-package (SiP)

Abstract: Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.

Development of a novel polymer–metal nanocomposite obtained through the route of in situ reduction for integral capacitor application

Abstract: Metal nanoparticles exhibit a number of interesting characteristics, including unique physical, chemical, optical, magnetic, and electric properties. Numerous investigations have exploited their properties in a readily usable form by incorporating them into polymers. The current focus of interest is the behavior of such polymer nanocomposites near the percolation loading levels of the metal nanoparticles. This material is particularly suitable for the new integral passive technology. Discrete capacitors are used in many applications, such as noise suppression, filtering, tuning, decoupling, bypassing, termination, and frequency determination, and they occupy a substantial amount of surface area on a substrate. Thus there are limitations in the number of capacitors that can be placed around the chip. Integral passive components are gradually replacing discrete components because of the inherent advantages of improved electrical performance, increased real estate on the printed wiring board, miniaturization of interconnect distance, reduced processing costs, and efficient electronics packaging. For integral capacitors, polymer composite material has emerged as a potential candidate because it meets the requirements of low processing temperature and reasonably high dielectric constant. Yang and Wong, whose patent was filed in 2001, demonstrated novel integral passive component materials with extraordinarily high dielectric constants (K > 1000) and high reliability performance. These materials are characterized by high dielectric constant based on the mechanism of interfacial polarization, although they need precision filler concentration control. The current study overcomes this drawback and produces the composite through an in situ reduction in an epoxy matrix. Material characterization was done through TEM, SEM, X-ray analysis, and energy-dispersive analysis for X rays. © 2004 Wiley Periodicals, Inc. J Appl Polym Sci 93: 1531–1538, 2004

Thin film integration of passives - single components, filters, integrated passive devices

Abstract: The increasing demands on future electronic products require more efficient system integration technologies. Especially the package density gap at board level with the high integrated circuits (ICs) on the one hand and the discrete passive components on the other has to be closed by new packaging technologies which integrate the passive components into the substrate, an interposer or the IC itself. This paper presents investigations for the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB). Technologies from wafer level packaging were adapted for manufacturing of the integrated components. The examinations were carried out with special focus on integrated coils and passive filter structures. Build up, design, processing as well as results of the electrical characterization of the integrated components are described in detail. Furthermore, an integrated passive device (IPD) for application as a filter element in the Bluetooth band is presented.

Towards roll-to-roll fabrication of electronics, optics, and optoelectronics for smart and intelligent packaging

Abstract: Embedding of optoelectrical, optical, and electrical functionalities into low-cost products like packages and printed matter can be used to increase their information content. These functionalities make also possible the realization of new type of entertaining, impressive or guiding effects on the product packages and printed matter. For these purposes, components like displays, photodetectors, light sources, solar cells, battery elements, diffractive optical elements, lightguides, electrical conductors, resistors, transistors, switching elements etc. and their integration to functional modules are required. Additionally, the price of the components for low-end products has to be in cent scale or preferably below that. Therefore, new, cost-effective, and volume scale capable manufacturing techniques are required. Recent developments of liquid-phase processable electrical and optical polymeric, inorganic, and hybrid materials - inks - have made it possible to fabricate functional electrical, optical and optoelectrical components by conventional roll-to-roll techniques such as gravure printing, embossing, digital printing, offset, and screen printing on flexible paper and plastic like substrates. In this paper, we show our current achievements in the field of roll-to-roll fabricated, optics, electronics and optoelectronics. With few examples, we also demonstrate the printing and hot-embossing capabilities of table scale printing machines and VTT Electronic's 'PICO' roll-to-roll pilot production facility.

Application of Au-Sn eutectic bonding in hermetic RF MEMS wafer level packaging

Abstract: Recently the strong demands in wireless communication requires expanding development for the application of RF MEMS (Radio Frequency micro electro mechanical systems) sensing devices such as micro-switches, tunable capacitors because it offers lower power consumption, lower losses, higher linearity and higher Q factors compared with conventional communications components. To accelerate commercialization of RF MEMS products, development for packaging technologies is one of the most critical issues should be solved beforehand. Packaging for RF MEMS is more challenging compared with conventional IC (integrated Circuit) Packaging technologies because it has both electrical and mechanical component, a low temperature, and hermetic wafer level packaging technology is needed for RF MEMS device. Au-Sn metallization system has been successfully utilize for flip chip bonding in many applications such as optoelectronic packaging and microwave device because of their high strength, good wetting behaviors, and resistance for thermal fatigue compared with conventional Pb/Sn solder system. Au-Sn eutectic bonding is considered to be a promising low temperature, wafer level bonding technology. In this paper, Au-Sn eutectic bonding for RF MEMS application is presented, a closed square loop was designed for the bonding structure, test vehicle was prepared for DOE (Design of experiment) process for the optimization of bonding parameters, and bonding temperature and applied load are found to be the most critical parameters for the bonding result, bonding can be done at a relative low temperature below 300/spl deg/C. For bonded samples, shear strength, warpage, insertion loss and hermetic tests etc. are performed for the evaluation of bonding quality, AES (Auger Electron Spectrum) and SEM (Scanning Electron Microscopy) was also made to investigate the microstructure of bonded interface, and reliability test such as thermal shock and high temperature, high humidity storage test was performed for the evaluation of bonding quality.

Localized induction heating solder bonding for wafer level MEMS packaging

Abstract: This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. The electroplated magnetic film was heated up using the induction heating, and leaded to solder reflow. It took only several seconds to complete the solder reflow and bonding process. The measurement results showed that the temperature of device region was only 110/spl deg/C during heating. Due to the solder reflow and electroplating technique, hermetic seal of the packaged device is achieved. The bonding strength is up to 18 MPa. In addition, the electroplated thick film also performed as a spacer. In applications, the integration the MUMPs devices with the proposed packaging techniques were demonstrated.

Design optimization and reliability of PWB level electronic package

Abstract: As the Electronic Packaging industry develops technologies for fabrication of smaller, faster, economical and reliable products; thermal management and design play an important role. The major part of the failures of the electronic components is temperature related. During thermal cycling, fatigue failures are caused due to mismatch of coefficient of thermal expansion (CTE) of different materials present in the components. Increased power dissipation and density in modern electronics system require efficient and intelligent design and thermal management strategies to ensure the reliability of electronic products. This paper discusses the reliability and design optimization of a generic Printed Wiring Board (PWB) level electronic package under thermal cycle loading. Finite element tool ANSYS is used to estimate the cycles to fatigue failure of solder joint of the package coupled with optimization module present in ANSYS for providing the details on determining optimal design parameters which affect the product reliability. Combining finite element analysis with optimization would significantly reduce the design time and increases the product reliability. Four model characteristics: PWB core in-plane Young's Modulus, PWB core in-plane coefficient of thermal expansion, PWB core thickness and the stand-off solder joint height are chosen as the optimization inputs (design variables) that ensure higher reliability and improved performance of the assembled product. The objective of the optimization is to improve the fatigue life of solder joints of the package. Sub approximation, Design of Experiment (DoE) and Central Composite Design based Response Surface Modeling Methodology are used to study the effects of each design variables on the fatigue life.

New high temperature polymer thin coating for power electronics

Abstract: A new development in the area of vapor phase deposited conformal and protective coatings, which offers solutions to many existing packaging and reliability challenges of power electronic component industry. A newly developed product, Parylene HT (W.R. Dolbier Jr. et al., 1998), possesses unique properties compared to all existing Parylenes and other vapor phase coatings. Experimental results and trial runs demonstrate the ability of Parylene HT coating to meet the growing requirements of higher dielectric capabilities, higher temperature integrity and mechanical processing etc. of dynamic power electronic industry. Parylene HT can easily be applied on stators, cores, torrids, capacitors, inductors, power supply electronics, batteries and ceramics for high performance and reliability.

Piezoresistive MEMS pressure sensor and packaging for harsh oceanic environment

Abstract: We report a fabrication and packaging approach for a piezoresistive micro electro mechanical (MEMS) pressure sensor designed to operate up to a depth of hundreds of meters under harsh seawater conditions. The pressure values at such depths would typically be in the range of 3000 psi and the temperature conditions would vary from as low as -5/spl deg/C to 60/spl deg/C. The sensor essentially consists of an array of silicon diaphragms 20-60 /spl mu/m in thickness with selective regions diffused with boron (p-type) that act as piezoresistors. The packaging solution involves a wafer-level and chip scale interconnection, approach taking into consideration appropriate material selection for harsh oceanic environments. The packaged pressure sensor is tested in a simulated harsh oceanic environment. Functional tests are performed in a custom-built pressure chamber, where the deep-sea water conditions were simulated (approximately depth of 1000 m). The tests demonstrated excellent mechanical integrity of the packaged device.

Low-cost and low-electromagnetic-interference packaging of optical transceiver modules

Abstract: The low-cost and low-electromagnetic-interference (EMI) packaging of optical transceiver modules employing housings of plastic composites are developed and fabricated. Optical transceiver modules fabricated by the plastic composites with transmission rates of 1.25 and 2.5 Gb/s are tested to evaluate the electromagnetic (EM) shielding against emitted radiation from the plastic packaging. The results show that these packaged optical transceiver modules with their high shielding effectiveness (SE) are suitable for use in low-cost and low-EMI Gigabit Ethernet lightwave transmission systems. By comparison of cost, weight, and shielding performance for optical transceiver modules fabricated by the housings of nylon and liquid-crystal polymer with carbon fiber filler composites, woven continuous carbon fiber (WCCF), and nanoscale hollow carbon nanocapulses (HCNCs) epoxy composites, the WCCF composite shows lower cost, lighter weight, and higher EM shielding than the other types of composites. Future studies may develop the low-cost and low-EMI optical transceiver modules using nanoscale HCNCs that have the combination of excellent physical and mechanical properties, light weight, and thinness compared with the conventional fabrication techniques.

High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging

Abstract: This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 μm were etched through on a 4-inch and 550 μm-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates quickly releasing after copper-interconnections electroforming. Compared to the tedious wet etching or mechanical polishing process, this peel-off relasing process provides a simpler way. After another lithography process, mushroom shape eutecic solder bumps (63Sn/37Pb) were directly electroformed on the top of each copper interconnection with the height of 100 μm, and reflowed at 200 °C for 5 min to form solder spheres. The feasibility of making highly dense and uniform electrical interconncetions has been successfully demonstrated on the wafer with fabricated micro temperature sensors. The estimated resistance for the copper-column of different diameters are characterized lower than 13.1 mΩ and this process provides a bump density up to 9648 interconnects/cm2.

Wafer bonding using microwave heating of parylene for MEMS packaging

Abstract: This paper describes a novel wafer bonding technique using microwave beating of parylene intermediate layers. The bonding is achieved by parylene deposition and thermal lamination using microwave heating. Variable frequency microwave heating provides uniform, selective, and rapid heating for parylene intermediate layers. The advantages of this bonding technique include short bonding time, low bonding temperature, relatively high bonding strength, less void generation, and low thermal stress. In addition, the intermediate layer material, parylene, is chemically stable and biocompatible. This bonding technique can be used for structured wafers as well because parylene provides a conformal coating. Therefore this is a very attractive bonding tool for many MEMS devices. The bonding strength and uniformity were evaluated using diverse tools. Fracture mechanisms and the effects of bonding parameters and an adhesion promoter were investigated as well. The bonding with a structured wafer was also successfully demonstrated.

Optical I/O technology for digital VLSI

Abstract: We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8 Gb/s aggregate data rate).

Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

Abstract: The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.

Integrated Module Board (IMB); an advanced manufacturing technology for embedding active components inside organic substrate

Abstract: One of the main questions and challenges in current electronics manufacturing and packaging development is how to integrate mote functions into the same or even smaller size. The electrical performance and the number of functions of every new product generation have increased and at the same time the size has decreased. Due to this the packaging density of the products has increased quite rapidly during past years. At the same time there is a need for better electrical properties of the package and the interconnection itself. This development has caused big challenges for the used packaging and manufacturing technologies. With traditional technologies it has become more difficult to increase the packaging density. To meet these requirements Integrated Module Board (IMB) technology has been developed. In the Integrated Module Board technology active components are embedded inside a printed wiring board (PWB) or other organic substrate. The IMB process combines PWB manufacturing, component packaging and component assembly into a single manufacturing process flow. The manufacturing process allows embedding an entire product or some of its functional parts inside the substrate. All interconnections between the IC and the substrate are done simultaneously using an electroplating process. The IMB technology enables high interconnection density with good reliability. In this paper an overview of IMB technology, its technological capability and electrical performance are presented.

An SU-8 liquid cell for surface acoustic wave biosensors

Abstract: One significant challenge facing biosensor development is packaging. For surface acoustic wave based biosensors, packaging influences the general sensing performance. The acoustic wave is generated and received thanks to interdigital transducers and the separation between the transducers defines the sensing area. Liquids used in biosensing experiments lead to an attenuation of the acoustic signal while in contact with the transducers. We have developed a liquid cell based on photodefinable epoxy SU-8 that prevents the presence of liquid on the transducers, has a small disturbance effect on the propagation of the acoustic wave, does not interfere with the biochemical sensing event, and leads to an integrated sensor system with reproducible properties. The liquid cell is achieved in two steps. In a first step, the SU-8 is precisely patterned around the transducers to define 120 μm thick walls. In a second step and after the dicing of the sensors, a glass capping is placed manually and glued on top of the SU-8 walls. This design approach is an improvement compared to the more classical solution consisting of a pre-molded cell that must be pressed against the device in order to avoid leaks, with negative consequences on the reproducibility of the experimental results. We demonstrate the effectiveness of our approach by protein adsorption monitoring. The packaging materials do not interfere with the biomolecules and have a high chemical resistance. For future developments, wafer level bonding of the quartz capping onto the SU-8 walls is envisioned.

Effects of the low loss polymers on the dielectric behavior of novel aluminum-filled high-k nano-composites

Abstract: Passive components, active components, and interconnecting substrates are the fundamental building blocks for an electronic system, and nowadays, a large percentage of the printed circuit board (PCB) surface area is taken up by the surface-mounted discrete passive components. Embedding these discrete components into the board structure has become the primary method to further miniaturize electronic systems. Besides the size reduction, embedded passives offer many other advantages. Reduced cost and improved electrical performance can be expected, and are actually another two major driving forces of embedded passive technology. To enable embedded passives, materials that satisfy the requirements of fabrication, electrical performance, and mechanical performance need to be developed. We report the innovative development of a low-cost high dielectric constant polymer-based composite that combines the advantages of polymer-ceramic and polymer-metal systems for embedded capacitor application. This novel material uses low cost self-passivated aluminum particles as the filler for the polymer composites. The thin self-passivated Al/sub 2/O/sub 3/ layer forms a nanoscale insulating boundary outside of the metallic spheres, which has dramatic influence on the electrical behavior of the resulting composites. The nanoscale insulating oxide layer allows the aluminum composites to have a high dielectric constant as a percolation system; on the other hand, the insulating oxide layer confines the electrons within an aluminum particle, thus keeping a very low loss of the composites.

Integrating nano carbontubes with microchannel cooler

Abstract: Providing effective and compact heat removal solutions is an essential element of the electronics packaging approach and its importance increases as the trend in the electronics industry moves towards higher packaging density and more severe operation conditions. Many new thermal removal techniques have been developed in response to this situation, among which microchannel liquid cooling systems have been considered as one of the very promising cooling solutions. Its major advantage includes the high heat transfer coefficient and possible wafer-level integration with chips. However, the high-pressure drop associated with microchannel flow prevents it to be employed in a fluid loop with micro-pump due to the pumping power limit. Enhancing the thermal exchange rate between substrate and coolant is a straightforward method to overcome this problem. The present work proposes two plausible methods to integrate high-thermal conductive nanotubes with existing microchannel coolers for enhancement in cooling capability. The first one is to replace the silicon fins with nanotube fins. Since nanotubes have extremely high thermal conductivity, the pin-to-coolant temperature difference can increase further and more heat can be transferred to the coolant. The second method is to grow aligned nanotubes on the whole thermal exchange surface of the groove where the coolant flows. Each nanotube stands separately and acts as a tiny pin, which dramatically increases the thermal exchange area. The theoretical part consists of a preliminary numerical study to determine the highest possible heat transfer capability of the nanotube enhanced microchannel cooler and how its performance is affected by geometrical parameters like channel width and length.

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

Abstract: The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform. The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 μm lines/space widths and 40 μm pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive. This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/∘C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.