Showing papers on "Electronic packaging published in 2005"

Electronic packaging including die with through silicon via

Abstract: An apparatus, method, and system for electronic device packaging having stacked dice are disclosed herein. A first die has a through silicon via formed therethrough. A second die is landed on the through silicon via of the first die. A mount having a lead is coupled to the through silicon via of the first die.

Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection

Abstract: This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of lowtemperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ~80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications.

Localized induction heating solder bonding for wafer level MEMS packaging

Abstract: This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

Self-assembly for microscale and nanoscale packaging: steps toward self-packaging

Abstract: The packaging of microelectromechanical systems (MEMS) and nanoscale devices constitutes an important area of research and development that is vital to the commercialization of such devices. Packaging needs of these devices include interfaces to nonelectronic domains; integration of structures, devices, and subsystems made with incompatible fabrication processes into a single platform; and the ability to handle a very large numbers of parts. Although serial, robotic assembly methods such as pick-and-place have allowed significant manufacturing feats, self-assembly is an attractive option to tackle packaging issues as the size of individual parts decreases below 300 /spl mu/m. In this paper, we review advances made in the usage of self-assembly for packaging and potential directions that growth in this area can assume. In the micrometer scale, we review the use of capillary forces, gravity, shape recognition, and electric fields to guide two- and three-dimensional self-assembly processes. In the nanoscale, we survey the usage of self-assembled molecular monolayers to solve current packaging issues, DNA hybridization for guiding self-assembly processes of nanoscale devices, and methods used to package nanowires or nanotubes into electronic circuits. We conclude with an example of a nanoscale biosensor which directly incorporates the concept of its package into its fabrication process. Even though the idea of a fully self-packaging system has not been demonstrated to date, the body of work reviewed and discussed here presents a solid foundation for the pursuit of this goal.

Design considerations and technology assessment of phased-array antenna systems with RF MEMS for automotive radar applications

Abstract: Planar array antennas are attractive for use in future automotive radar systems due to their flexibility in design and control of radar beams. The complexity and cost of a radar front-end phased array can be decreased by applying a beam-steering/switching concept, which reduces the number of parallel RF and baseband signal paths. RF-microelectromechanical systems (MEMS) subsystems are employed because of their excellent RF properties and potential low-cost manufacturability. We present design considerations for prototypical automotive applications of RF-MEMS-based automotive radar front-ends using phased-array antennas based on phase shifters or a Rotman lens. The single RF-MEMS switch is optimized with respect to its RF and thermomechanical behavior taking into account automotive requirements. The respective RF-MEMS subsystems, i.e., phase shifters and single-pole-multiple-throw switching networks are presented in conjunction with packaging and mounting approaches. We evaluate two different wafer-level packaging technologies using glass-frit sealing or polymer sealing. Finally, functional packaged devices are demonstrated: a glass-frit-sealed and flip-chip-mounted RF-MEMS switch and a benzocyclobutene-packaged single-pole-quadruple-throw switch network.

Packaging of bio-MEMS: strategies, technologies, and applications

Abstract: Biomicroelectromechanical systems (bio-MEMS) are MEMS which are designed for medical or biological applications. As with other MEMS, bio-MEMS frequently, have to be packaged to provide an interface to the macroscale world of the user. Bio-MEMS can be roughly divided in two groups. Bio-MEMS can be pure technical systems applied in a biological environment or technical systems which integrate biological materials as one functional component of the system. In both cases, the materials which have intimate contact to biological matter have to be biocompatible to avoid unintentional effects on the biological substances, which in case of medical implants, could harm the patient. In the case of biosensors, the use of nonbiocompatible materials could interfere with the biological subcomponents which would affect the sensor's performance. Bio-MEMS containing biological subcomponents require the use of "biocompatible" technologies for assembly and packaging; e.g., high temperatures occurring, for instance, during thermosonic wire bonding and other thermobonding processes would denature the bioaffinity layers on biosensor chips. This means that the use of selected or alternative packaging and assembly methods, or new strategies, is necessary for a wide range of bio-MEMS applications. This paper provides an overview of some of the strategies, technologies, and applications in the field of bio-MEMS packaging. It includes the following: strategies for the partitioning of subsystems within integrated microsystems for (bio)chemical analysis/synthesis; methods for microassembly of bio-MEMS; technologies for bonding of polymer bio-MEMS components; packaging of miniature medical devices; packaging of biosensors for in vitro applications; packaging of micropumps as a bio-MEMS component. The applications discussed are derived from different fields to demonstrate the plethora of bio-MEMS considerations. In commercial production, packaging is possibly the major cost factor of bio-MEMS-based products, and its development requires special attention.

Introduction to active food packaging technologies

Abstract: Publisher Summary This chapter focuses on active food packaging, which performs some desired function other than merely providing a barrier to the external environment. Active packaging is normally designed to address one property or requirement of the food or beverage. The property normally chosen is that which is most critical as the first limiter of quality or shelf life. To this extent, active packaging is provided to fine-tune the properties of the packaging to meet the requirements of the food. This is not different from the normal aim of the packaging technologist to match the requirements of the food with the properties of the packaging. The choice of the form to be taken by the active packaging is made based on three broad considerations. The most important requirement is of the food, followed by the packaging format, and the requirements of the active agent. The demands of the food can be visualized by considering the potential application of gas exchange in a retail pack of ground beef removal of oxygen, or addition of carbon dioxide may be the chosen method of reducing spoilage by aerobic microorganisms.

Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging

Abstract: Product level assessment of drop and shock reliability relies heavily on experimental test methods Prediction of drop and shock survivability is largely beyond the state-of-art However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging Data on damage progression under transient-shock and vibration in both 955Sn40Ag05Cu and 63Sn37Pb ball-grid arrays has been presented Component types examined include flex-substrate and rigid substrate ball-grid arrays Dynamic measurements like acceleration, strain and resistance are measured and analyzed using highspeed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level The approach is scalable to application at system-level Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope Model predictions have been correlated with experimental data for both leaded and leadfree ball-grid arrays

Three-dimensional packaging for power semiconductor devices and modules

Abstract: Demands for increasing power density and levels of functional integration in switch-mode power converters require power electronics manufacturers to develop innovative packaging solutions for power semiconductor devices and modules. Three-dimensional (3-D) packaging techniques offer the potential of lower resistance, higher current handling capability, smaller volume, better thermal management capability, and high reliability. In this paper, we present the constructions and some electrical and thermomechanical analyses of four 3-D packaging approaches that have been developed within the Center for Power Electronics Systems-an NSF Engineering Research Center.

Silicon-based Packaging Platform for Light Emitting Diode

Abstract: A novel concept of silicon-based packaging platform with microreflector and embedded electrode-guided interconnections was development for a package component of a light-emitting diode (LED). TracePro and ANSYS software were respectively used to understand the optical and thermal characteristics of the package component. Simulation results show the microreflector at several certain specific dimensions can be used to achieve high brightness, and the carrier made of silicon wafer compared with that of aluminum stage can minimize the thermal stresses caused by mismatch of thermal expansion coefficient. The novel packaging platform was fabricated by silicon bulk micromachining and solder reflow techniques. Various solutions in fabricating embedded solder interconnections were explored to accomplish the electrode-guided interconnections. Experimental results show the method using solder paste reflow can achieve better yield and performance. The electrical resistances of such solder interconnections with the height of 100 mum were measured to be less than 5 Omega. As such, this technique can be applied broadly in packaging for conventional optoelectronic semiconductor devices such as laser diodes and image sensors

A Transparent, High Barrier, and High Heat Substrate for Organic Electronics

Abstract: The use of plastic film substrates for organic electronic devices promises to enable new applications, such as flexible displays and conformal lighting, and a new low-cost paradigm through high-volume roll-to-roll fabrication. Unfortunately, presently available substrates cannot yet deliver this promise because of the challenge in achieving the required combination of optical transparency, impermeability to water and oxygen, mechanical flexibility, high-temperature capability, and chemical resistance. Here, we describe the development and performance of a plastic substrate comprising a high heat polycarbonate film combined with a unique transparent coating package that is aimed at meeting this challenge.

Integrated nanotube microcooler for microelectronics applications

Abstract: Providing effective and compact heat removal solutions is an essential element of the electronics packaging approach and its importance increases as the trend in the electronics industry moves towards higher packaging density. Many new thermal removal techniques have been developed. Liquid cooling has been considered as one of the very promising solutions. Its major advantages include the high heat transfer coefficient and possible wafer-level integration with chips. The present work reports the integration of nanotubes which have extremely high thermal conductivity in comparison to conventional microchannel coolers for enhancement in cooling capability. By using lithography techniques, chemical vapor deposition and adhesive bonding; a microcooler with two-dimensional nanotube fins was manufactured. Though it has fairly low cooling capability at the present stage, this new cooler has shown promise in the experimental characterization. Additionally, further modifications have been proposed and some possible reliability concerns were sited.

An approach to deal with packaging in power electronics

Abstract: Current packaging technology in power electronics is based on assembling pre-manufactured discrete components. Each component consists of a number of parts, manufactured in a variety of manufacturing processes. This has resulted in a diversity of construction parts and mutually incompatible manufacturing processes in a typical power electronic converter and has brought power electronics to the edge where it becomes extremely difficult to reduce the cost and size of power electronic converters. This also makes integration of power electronic converters difficult. In this paper, we present a way to improve the physical construction of power electronic converters by increasing level of integration and using multifunctional construction parts. integration and packaging are two important aspects of physical construction of power electronic converters. Both of them and their mutual relationship are discussed in the paper. Three quantities intended to evaluate integration level and volumetric utilization namely functional elements integration level, K/sub I/; packaging elements integration level K/sub P/; and volumetric packaging efficiency /spl eta//sub v/ are introduced. Based on these values, a number of techniques to increase the integration level are presented. A design process in the form of a flowchart intended to implement these techniques in concrete design cases is presented.

Optimization for chip stack in 3-D packaging

Abstract: We have been developing three-dimensional (3-D) packaging technology for forming through-type electrodes in chips that are then directly connected in stacks. The model examined in this study is defined by its simple structure. The structure was optimized for successful connection in a chip stack without degrading the features of the chips. The use of this structure enabled a stable and rigid connection, and a four-layer chip stack assembled on a ceramic substrate exhibited adequate thermal cycle performance. This paper discusses how the structure of terminals was optimized for chip stacking. A finished package assembled from static random access memory (SRAM) with through-type electrodes was confirmed to operate well and exhibit normal functioning.

Flexible cryo-packages for Josephson devices

Abstract: We have developed a method of bonding superconductive integrated-circuit chips to interchangeable, microwave-compatible, flexible cryo-packages. This "flip-chip on flex" technology will greatly improve the service life and reliability of our Josephson systems because the present press-contacts to the chip are replaced with directly soldered connections. The new method eliminates the most common failure mode for our Josephson chips, which has been the degradation and variation of the contact resistances of the chip pads due to mechanical wear upon repeated thermal cycles from 4/spl deg/K to room temperature. The superior microwave properties of this packaging provide improved operating margins for our devices. We have demonstrated the reliability of the bonds with repeated thermal cycling for 100% operational chips with 40 connections (67 410 Josephson junctions).

A low cost wafer-level MEMS packaging technology

Abstract: This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat cap, and can be applied to both surface and bulk micromachined structures. Encapsulation of high-g silicon-on-insulator resonators, and thick silicon gyroscopes and accelerometers are presented.

Theoretical and experimental Raman spectroscopy study of mechanical stress induced by electronic packaging

Abstract: The mechanical stress induced in Si chips by the packaging process (effect of die attach, flip chip bumping, etc.) is measured by micro-Raman spectroscopy. The measurements are performed on the [110] cross-section surface of the polished samples. This study shows that the current Raman formula for top-surface measurements cannot be used for cross-section measurements due to the anisotropic property of Si. The new formula for cross-section measurements is introduced in this paper. The experimental results are compared to finite element simulations. The Raman results correlate very well with the FE calculations. It shows that micro-Raman spectroscopy is a very interesting technique to study packaging induced stress in Si chips and to validate finite element calculations.

Compact packaging of optical and electronic components for on-board optical interconnects

Abstract: An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.

Advanced packaging shell for pocketable consumer electronic devices

Abstract: A method for encapsulating electronic components in consumer electronic devices is disclosed A sealed packaging shell for electronic components is created from a single monolithic piece of elastomeric material Electronic components, including a PCB, are hermetically encapsulated within the packaging shell during the process of its formation

Embedded conductor technology for micromachined RF elements

Abstract: A surface-micromachined, multilayer, embedded conductor fabrication process is presented. The process is based on high-aspect-ratio MEMS via formation and subsequent conformal/plate-through-mold metallization. Using this process, the fabrication of epoxy-embedded, high-Q electroplated RF inductors is demonstrated. This process has two attractive features. First, the embedded nature of these interconnects and inductors allows conventional handling and packaging of inductor/interconnect/chip systems without additional mechanical consideration for the inductor structure and without its significant electrical degradation after further packaging. Second, since the embedding material forms a permanent structural feature of the device, embedding materials that would otherwise be difficult to remove during the fabrication process are instead very appropriate for this technology. The epoxy-based implementation of this technology is low temperature and compatible with post-processing on CMOS foundry-fabricated chips or wafers. Multiple solenoid-type inductors with varying numbers of turns and core-widths are fabricated on a silicon substrate using this technology. A six-turn solenoid type inductor shows an inductance of 2.6 nH and a peak Q-factor of 20.5 at 4.5 GHz.

Method and apparatus for packaging an electronic chip

Abstract: An electronic packaging combines features of a MAP (molded array package) and a lead frame package. The package includes an electrically conductive substrate somewhat like a lead frame package but defines a grid of conductive pads rather than a multiplicity of leads as is common with a lead frame package. An electronic chip is attached to the top surface of the lead frame, and the output terminals of the electronic chip are individually electrically connected to selected connecting pads of the lead frame grid array. Both flip chips and wire bond chips may be connected to the grid array. The channels defining the grid of connecting pads extend part way through the conductive substrate and increase in width from the top surface of the lead frame to the bottom of the channel such that the molding compound is locked in place when it cures and hardens. The grid pads are then singulated by sawing or etching channels from the bottom surface of the lead frame substrate that correspond to the channels defining the connecting pads on the top surface.

Power electronic interconnects: skin- and Proximity-Effect-based frequency Selective-Multipath propagation

Abstract: Structural electromagnetic effects, attributed to the packaging and construction of power electronic converters, are often seen as detrimental and it is attempted to eliminate these "parasitics." This paper explores the utilization of some of these structural electromagnetic effects to achieve higher levels of functional integration in modules by obtaining low-pass filtering for various applications by controlling the material and geometry of selected interconnecting structures. Multipath propagation with frequency selective attenuation is one of the promising new technologies presented. Modeling and experimental results are given for a number of different cases showing promise for future integration into power electronic products as currently discussed in the literature. The conclusion reached from the research is that phenomena like the skin and proximity effect that are often considered as detrimental and to be avoided or minimized, can indeed be controlled and used to enhance the operation of power electronic systems.

Wafer level vacuum packaging of MEMS sensors

Abstract: A process has been developed for wafer level vacuum packaging MEMS sensors, which are fabricated from etched, single crystal silicon structures, anodically bonded to metallized glass wafers. Key objectives of the process design were to minimize the number of changes to sensor fabrication, insure a high level of vacuum integrity, and flexible enough to accommodate a wide range of sensor designs. Only a single change to the standard sensor fabrication is required to implement the vacuum sealing process. A seal ring of gold, 250 microns wide by 1 micron thick is applied around the perimeter of the sensor and its electrical contact pads. The key features of this vacuum sealing technology are incorporated in the silicon cap wafer. It is 200 microns thick and contains an array of cavities, 50 microns deep, which align with the MEMS devices on the glass wafer. The opposite side of the wafer is coated with 2000 angstroms of silicon dioxide and is arrayed with aluminum bond pads, which align with those on the sensor wafer. These pads are connected to the sensor by through wafer vias, which are coated with a layer of parylene, one micron thick. The parylene is applied in a vapor deposition process, and then an excimer laser is used to ablate it from the bottom of the vias to allow electrical connections to be made to the aluminum bond pads. The vias are metallized with an adhesion layer of 500 angstroms of titanium and a conduction layer of 2000 angstroms of gold. This metal is photo-patterned, to produce pads that align with those of the sensor, and then all exposed parylene is removed by reactive ion etching. This cap wafer is bonded to the sensor wafer in an ultra-high vacuum system with a base pressure of 10/sup -8/ Torr. The two wafers are held on electrostatic chucks, one of which is hinged, so that in the degas phase, both wafers can be cleaned in-situ with an ion gun. For bonding, the hinge is actuated to position the cap wafer above the sensor wafer. A pair of prisms is positioned between the wafers to allow them to be precisely aligned prior to sealing. The wafers are bonded together by heating them to 300 /spl deg/C and actuating a pair of ball screws, which clamps them together under a load of 500 Newtons. The load and temperature is maintained for one hour to allow the gold of the sensor seal ring to react with the silicon of the cap wafer. The bonded pair is slowly cooled under load to complete the sealing process. The ultimate goal of this sealing approach is to use the control ASIC chip that is paired with the sensor, as the cap structure. This would minimize the length of signal paths between the ASIC and sensor, while realizing a very compact vacuum package.

Soldering method using longitudinal ultrasonic

Abstract: An efficient ultrasonic soldering method of inserting the metal bumps into the solder is investigated in this work for electronic packaging. The effects of the process parameters such as the ultrasonic frequency, amplitude, dimensions of the metal bump and solder are analyzed through the viscoelastic modeling. The ultrasonic soldering was conducted using the Cu and Au bumps, and the acceptable bonding condition was determined from the tensile strength. Localized heating of the solder was achieved and the stirring action due to the ultrasonic influences the bond strength and microstructure of the eutectic solder. Since higher temperature is obtained with smaller solder, the proposed ultrasonic soldering method appears to be applicable to the high-density electronic packaging.

RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

Abstract: Design, modeling, and characterization of inductors embedded in a package substrate promising higher quality factor (Q) and lower cost than on-chip inductors is described. In addition to the problem of large conductor losses, on-die inductors with or without magnetic materials consume considerable die area and require the removal of the first-level interconnect bumps beneath them to maintain a reasonably high Q value. Moving inductors to the package eliminates the need for bump array depopulation and, thus, mitigates the potential reliability problems caused by voids in the epoxy underfill between the die and the substrate. Competency developed to design, fabricate, and characterize inductors based on standard organic flip-chip packaging technology is described. Physical design details along with measurement procedures and results are discussed. In addition, modeling techniques for achieving good correlation to measured data are included.

Vacuum Web Coating - State of the Art and Potential for Electronics

Abstract: Going flexible seems to be a major trend for a variety of electronic applications such as displays, printed circuit boards, solar cells, and solid-state lighting. Driving forces, which may often include the function of "flexibility," are the potential to build units with less thickness and with less weight or the ability for very-large-area applications. Last but not least, there is the need for a remarkable reduction of production costs, which can be fulfilled by changing the production process from sheet processing to roll to roll. The first vacuum web coater was built 70 years ago, and vacuum web coating is currently used for a wide variety of applications. In the packaging industry, aluminum coating is primarily used for barrier improvement of plastic substrates. Such coatings are deposited with an evaporation process in machines of up to 4-m coating widths on rolls up to 60 000-m length and at coating speeds of more than 16 m/s. For capacitor production, thin webs with thicknesses down to the submicrometer range are vacuum-coated with aluminum, silver, or zinc layers, and uncoated stripes or patterns are also needed. Vacuum-coated web-shaped substrates can also be used for antireflective, antistatic function in the front of monitors, as window films for cars and architectural applications or as front electrodes for touch panels as a few examples. Different coating tools such as evaporation, sputtering, plasma-enhanced chemical-vapor deposition (PECVD), as well as pretreatment tools and inline layer measurement systems are available. Many of the currently available tools and processes existing in the web coating industry may become useful for upcoming electronic applications, but special demands for these new applications, such as exact area tracking, zero defects, roll-to-roll masking, and reduced substrate temperature during coating, require further development of machine design and process technology. This paper will summarize the state of the art of vacuum w