Showing papers on "Electronic packaging published in 2006"

Recent advances of conductive adhesives as a lead-free alternative in electronic packaging: Materials, processing, reliability and applications

Abstract: Tin–lead solder alloys are widely used in the electronic industry. They serve as interconnects that provide the conductive path required to achieve connection from one circuit element to another. There are increasing concerns with the use of tin–lead alloy solders in recognition of hazards of using lead. Lead-free solders and electrically conductive adhesives (ECAs) have been considered as the most promising alternatives of tin-lead solder. ECAs consist of a polymeric resin (such as, an epoxy, a silicone, or a polyimide) that provides physical and mechanical properties such as adhesion, mechanical strength, impact strength, and a metal filler (such as, silver, gold, nickel or copper) that conducts electricity. ECAs offer numerous advantages over conventional solder technology, such as environmental friendliness, mild processing conditions (enabling the use of heat-sensitive and low-cost components and substrates), fewer processing steps (reducing processing cost), low stress on the substrates, and fine pitch interconnect capability (enabling the miniaturization of electronic devices). Therefore, conductive adhesives have been used in liquid crystal display (LCD) and smart card applications as an interconnect material and in flip–chip assembly, chip scale package (CSP) and ball grid array (BGA) applications in replacement of solder. However, no currently commercialized ECAs can replace tin–lead metal solders in all applications due to some challenging issues such as lower electrical conductivity, conductivity fatigue (decreased conductivity at elevated temperature and humidity aging or normal use condition) in reliability testing, limited current-carrying capability, and poor impact strength. Considerable research has been conducted recently to study and optimize the performance of ECAs, such as electrical, mechanical and thermal behaviors improvement as well as reliability enhancement under various conditions. This review article will discuss the materials, applications and recent advances of electrically conductive adhesives as an environmental friendly solder replacement in the electronic packaging industry.

Advanced electronic packaging

Abstract: Chapter 1: Introduction and overview of microelectronic packaging. Chapter 2: Materials for microelectronic packaging. Chapter 3: Processing technologies. Chapter 4: Organic printed circuit board materials and processes. Chapter 5: Ceramic substrates. Chapter 6: Electrical considerations, modeling, and simulation. Chapter 7: Thermal considerations. Chapter 8: Mechanical design considerations. Chapter 9: Discrete and embedded passive devices. Chapter 10: Electronic package assembly. Chapter 11: Design considerations. Chapter 12: Radio frequency and microwave packaging. Chapter 13: Power electronics packaging. Chapter 14: Multichip and three-dimensional packaging. Chapter 15: Packaging of MEMS and MOEMS: challenges and a case study. Chapter 16: Reliability considerations. Chapter 17: Cost evaluation and analysis. Chapter 18: Analytical techniques for materials characterization.

3D System Integration Technologies

Abstract: Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

The rise of the 3rd dimension for system intergration

Abstract: Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP (`above' passivation), approach and a foundry level (`below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail

Evaluation of Die Stress in MEMS Packaging: Experimental and Theoretical Approaches

Abstract: The device performance of microelectromechanical system (MEMS) inertial sensors such as accelerometers and gyroscopes is strongly influenced by the stress developed in the silicon die during packaging processes. This is due to the die warpage in the presence of the stress. It has previously been shown that most of the stress is generated during a die-attach process. In this study, we employ both experimental and theoretical approaches to gain a better understanding in a stress development induced during the packaging processes of a small silicon die (3.5times3.5 mm2). The former approach is accompanied with an optical profilometer while the latter part by a finite element analysis and an analytical model. A specific emphasis is given to the effects of structural parameters such as the die-attach adhesive thickness and material properties on the stress development. The results from all three approaches show good agreement, in that more compliant and thicker adhesives offer great relief in the stress development, as well as bend the die convex downward from its central location. A stress model proposed from this study not only provides a diagnostic tool for very small stress-sensitive devices, but it will also present a design tool for low-stress MEMS packaging systems

Determination of the complex permittivity of packaging materials at millimeter-wave frequencies

Abstract: The focus of this paper is the determination of the complex permittivity of chip packaging materials at millimeter-wave frequencies. After a broad overview of existing measurement techniques, three methods will be presented that have been established for the dielectric property determination of substrate, as well as mold materials (encapsulants, under-fill, etc.) in the millimeter-wave frequency range. First, the open resonator used here will be briefly described. It allows accurate determination of the dielectric constant and loss of thin sheet substrate materials from below 20 GHz to above 100 GHz. Second, a filled waveguide method is explained in detail. The setup used here can determine the complex dielectric properties of mold materials from 70 to 100 GHz. Third, the method based on covered transmission lines will be described in detail. The used lines allow measurements from below 40 GHz to approximately 90 GHz. Verification of all three methods will be provided by inter-comparison and comparison to values from the literature. Additionally, results for several typical substrate and mold materials that are available for millimeter-wave packaging will be shown and discussed.

Packaging of MMICs in multilayer LCP substrates

Abstract: A 13-25-GHz GaAs bare die low noise amplifier is embedded inside a multilayer liquid crystal polymer (LCP) package made from seven layers of thin-film LCP. This new packaging topology has inherently unique properties that could make it an attractive alternative in some instances to traditional metal and ceramic hermetic packages. LCP is a near-hermetic material and its lamination process is at a relatively low temperature (285degC versus >800degC for ceramics). The active device is enclosed in a package consisting of several laminated C02 laser machined LCP superstrate layers. Measurements demonstrate that the LCP package and the 285degC packaging process have minimal effects on the monolithic microwave integrated circuit radio frequency (RF) performance. These findings show that both active and passive devices can be integrated together in a homogeneous laminated multilayer LCP package. This active/passive compatibility demonstrates a unique capability of LCP to form compact, vertically integrated (3-D) RF system-on-a-package modules

novel Rare-Earth-containing Lead-Free Solders with Enhanced ductility*

Abstract: Severallead-free material systems are availableas replacements for traditional lead-based solders in microelectronic packaging, including near-eutectic combinations oftin-rich alloys. Although these materials have superior mechanical properties as compared to the Pb-Sn system, much work remains in developing these materials for electronic packaging. Small additions of rare-earth elements have been shown to refine the microstructure of several lead-free solder systems, thus improving their mechanical properties. This study investigated the effect of the addition of lanthanum on the melting behavior, microstructure, and shear strength of an Sn-3.9Ag-0.7Cu alloy. The influence of LaSn3 intermetallics on microstructural refinement and damage evolution in these novel solders is discussed.

Reliability in MEMS Packaging

Abstract: Cost effective packaging and robust reliability are two critical factors for successful commercialization of MEMS and microsystems While packaging contributes to the effective production cost of MEMS devices, reliability addresses consumer's confidence in and expectation on sustainable performance of the products There are a number of factors that contribute to the reliability of MEMS; packaging, in particular, in bonding and sealing, material characterization relating to operating and environmental conditions, credible design considerations, the techniques for mitigating intrinsic stresses/strains induced by fabrications and testing for reliability are a few of these factors This paper will offer an overview of these factors with proposed resolutions to issues relating to the reliability of these products

Effects of fluid properties on dispensing processes for electronics packaging

Abstract: The fluid dispensing process has been widely employed in electronics packaging manufacturing to deliver fluid materials (such as epoxy, encapsulant, adhesive) on substrates or printed circuit boards (PCBs) for the purpose of die attachment, encapsulation, coating, or surface mounting. In this process, the fluid properties such as How behavior, surface tension, and contact angle can have a significant influence on the How rate of the fluid dispensed and the profile of fluid formed on the substrate or PCB, thereby affecting the quality of electronics packaging. At present, massive measurements are always required to characterize the fluid properties by using specific instruments, and the procedure of measuring is time-consuming. This paper presents a method upon which the fluid properties and their influence on the dispensing process can be readily identified from a few measurements of the process. By experiments, this method was proven to be not only cost and time effective but also promising for the investigation into the effects of fluid properties on the dispensing process.

Thermal design of high-power LED package and system

Abstract: In this paper we present thermal analysis of three kinds of ceramic package designs for high power LEDs and thermal characterization of high power LED array system. The analysis was made by transient thermal measurement and thermal simulation using the finite volume method (FVM). For the package design, thermal behaviors, as are described in thermal resistance, of the three packaging designs were compared and evaluated as functions of bulk thermal resistance, spreading resistance, and surface roughness. The deviation between the simulated results and measured data were attributed to the different surface roughness in the interfaces between the packaging components. For the system design, the emphasis is placed upon the investigation of junction temperature rise of LED array for a limited range of boundary conditions which include design effect of heat pipe, convection condition, and ambient temperature. It was found out that the measured junction temperatures and thermal resistance of LED array are increased with the input power and ambient temperature and decreased with the air velocity. An analytical thermal model analogous with an equivalent parallel circuit system was proposed and was verified by comparison with experimental data.

Vibrating RF MEMS for Timing and Frequency References

Abstract: This paper presents recent progresses on making vibrating RF MEMS oscillators for timing and frequency reference applications. Starting from the performance requirements of an oscillator in various systems, the key aspects of MEMS oscillators, including resonator design, oscillator performances, temperature compensation, packaging and integrations, are reviewed. Future directions of the research are also suggested at the end of the paper.

An all-glass chip-scale MEMS package with variable cavity pressure

Abstract: A dielectric, chip-scale MEMS packaging method is discussed. The packaging method uses wafer-to-wafer bonding of micromachined glass wafers with a reflowed, glass, sealing ring. The glass wafers are micromachined and have metal and silicon structures patterned on them with metal and fluidic feedthroughs. A variety of getters and sealing designs are disclosed to vary the pressure of the microcavity by many orders of magnitude from under 1 mTorr up to 1 atm (760 000 mTorr), enabling either vacuum or damped packaging of the device elements on the same chip. The final singulated, all-glass, chip-scale package can have electrical, optical/IR and fluidic interfaces. Applications for resonators, switches, optical sensors and displays are discussed.

Thermal Deformation Measurement by Digital Image Correlation Method

Abstract: Thermal-mechanical behavior of materials and reliability assessment of semiconductor packages are two of key issues in electronic packaging. Digital image correlation method is increasingly used for thermal deformation characterization in electronic packaging in recent years. For example, the deformation measurements of solder joints in various semiconductor packages have been reported in previous studies. However, the noise effects on measurement accuracy under thermal loading conditions have been less evaluated. When acquiring images of a specimen subjected to thermal loading in a chamber with glass window, the influences of the computer vision system, specimen surface condition, out-of-plane deformation and rigid body translation and rotation are required to be addressed. In this paper, such critical factors are evaluated during the calibration of a digital image correlation system. Proper measures are introduced to minimize the noise level. The thermal deformation measurement of a solder joint in a BGA (ball grid array) package is also demonstrated

Poly(dimethylsiloxane)-Based Packaging Technique for Microchip Fluorescence Detection System Applications

Abstract: A simplified integration process including packaging is presented, which enables the realization of the portable fluorescence detection system A fluorescence detection microchip system consisting of an integrated p-i-n photodiode, an organic light-emitting diode as the light source, an interference filter, and a microchannel was developed The on-chip fluorescence detector fabricated by poly(dimethylsiloxane) (PDMS)-based packaging had a thin-film structure A silicon-based integrated p-i-n photodiode combined with an optical filter removed the background noise, which was produced by an excitation source, on the same substrate The active area of the finger-type p-i-n photodiode was extended to obtain a higher detection sensitivity of fluorescence The sensitivity and the limit of detection (LOD; S/N=3) of the system were 0198 nA/muM and 10 muM, respectively

Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design

Abstract: During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mmtimes10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA

Motion stages for electronic packaging design and control

Abstract: This paper reviews the design and control progress of motion stages for electronics packaging, specifically, for wire bonding, due to its characteristics of high acceleration and high accuracy. The paper also introduces both conventional serial-type and new parallel-type motion stages. Several modeling techniques and many high performance control schemes are also reviewed

3D electronic packaging structure having a conductive support substrate

Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.

Advances in Vapor Pressure Modeling for Electronic Packaging

Abstract: Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders

Waveguide and packaging technology for optical backplanes and hybrid electrical-optical circuit boards

Abstract: Due to ever-faster processor clock speeds, there is a rising need for increased bandwidth to transfer large amounts of data, noise-free, within computer and telecommunications systems. A related requirement is the demand for high bit-rate, short-haul links. Here, optical transmission paths are a viable alternative to high-frequency electrical interconnections, whereby layers with integrated waveguides are particularly suitable. The reasons for this include that a higher connection density can be achieved and the power dissipation, as well as interference from electromagnetic radiation, are significantly lower. The article presents general considerations and the results of research conducted by the German BMBF Project NeGIT, into the manufacture of circuit boards with embedded polymer optical waveguides. The electrical-optical boards were fabricated using precise photolithographic processes and standard lamination methods. They possess the thermal stability necessary for manufacturing processes and operational conditions, in terms of both bond strength and the stability of the optical properties. As part of this project, a design of an optical coupling in the daughter card and board backplane interfaces was developed and is presented as the centerpiece of this study.

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Abstract: Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Ultra-lightweight, high efficiency SiC based power electronic converters for extreme environments

Abstract: Silicon-carbide (SiC) semiconductor devices have numerous potential advantages over their conventional silicon counterparts (i.e., higher switching frequencies, lower switching losses, higher temperature of operation, higher blocking voltages, higher thermal conductivity, radiation hardness, etc.). These advantages have sparked the birth of a new generation of power converters, distinguishing themselves from their ancestors with a higher efficiency and operating frequency, resulting in a marked increase in power density and a considerable reduction in weight. This paper explores the feasibility of developing a highly efficient, ultra-lightweight SiC based DC/DC converter, including the electrical design philosophy, high-temperature packaging approaches, high-temperature testing of several key components, and the overall high-temperature package design. This technology will have important implications in many weight-sensitive applications such as aircrafts, satellite and NASA space exploration program. In addition, this technology will be highly beneficial for electronics that must operate in a high-temperature environment such as those located in the outside of spacecraft probes and landers.

Advanced packaging materials for optical applications: bridging the gap between nm-size structures and large-area panel processing

Abstract: During the last two decades, nano-materials have been intensively investigated due to their wide range of properties, resulting in a variety of applications. In order to serve as advanced packaging material, from an industrial point of view emphasis has also to be on cost reduction either for the materials, the processes, or for both. Materials are searched for which enable processing and integration from a nm up to a cm scale. A particular class of low-cost nanoscale materials fulfilling this requirement are inorganic-organic hybrid polymers (ORMOCER®)1 which are synthesized by catalytically controlled hydrolysis/polycondensation reactions, resulting in storage-stable resins. Due to the variety of chemical and physical parameters, the material and processing properties which directly influence the resulting structure and thus the physical properties, can be varied over wide ranges. Upon synthesis, functional organic groups are introduced into the material which allows one to photochemically pattern the resins. The materials are capable to be patterned on a nm up to a cm scale, employing a variety of different micro- and nanopatterning methods such as, UV lithography, UV replication/lithography, laser-direct writing, or two-photon polymerization, in order to generate micro- and nano-optical components. While for most of the techniques the patterning has to be repeated several times in order to achieve multi-functional layers, the latter method allows one to directly write arbitrary 3D structures into the hybrid polymer material. The combination of chemically designed low-cost materials with tunable material parameters such as low optical absorption, tunable refractive index, good processibility, and high chemical, thermal and mechanical stability, is very attractive for (integrated) optical applications. Examples for application of the materials for microoptics as well as for optical back-planes generated by large-area processing will be given.

A Novel RF-Curing Technology for Microelectronics and Optoelectronics Packaging

Abstract: A novel open waveguide cavity resonator for the combined variable frequency microwave (VFM) curing of bumps, underfills and encapsulants, as well as the alignment of devices for fast flip-chip assembly, direct chip attach (DCA) or wafer-scale level packaging (WSLP) is presented This invention achieves radio frequency (RF) curing of adhesives used in microelectronics, optoelectronics and medical devices with potential simultaneous micron-scale alignment accuracy and bonding of devices using VFM technology The open oven cavity can be fitted directly onto a flip-chip or wafer scale bonder and, as such, will allow for the bonding of devices through localised heating thus reducing the risk to thermally sensitive devices

High-Performance Low-Cost 10-Gb/s Coaxial DFB Laser Module Packaging by Conventional TO-Can Materials and Processes

Abstract: High-performance low-cost 10-Gb/s coaxial DFB laser module packages made by conventional TO-Can materials and processes are developed and fabricated. The laser module has a built-in matching resistor to reduce the resonant phenomenon. In order to optimize the module's performance, a detailed equivalent circuit model is established to investigate both the DFB laser diode and the coaxial package comprehensively. This uncooled 10-Gb/s laser module operates at a high temperature of up to 105degC, and maintains an eye mask margin above 28% in the full operational temperature range to meet the stringent requirements of 10-Gb/s Ethernet for long-reach applications. This paper demonstrates that it is possible to fabricate cost-effective packages using existing low-cost TO-Can package technology while maintaining the high performance of the 10-Gb/s coaxial laser modules. Previously, the high-performance 10-Gb/s coaxial laser modules have only been available by using complicated design, customized components, and specialized fabrication process

A novel joint-in-via flip-chip chip-scale package

Abstract: It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the microvias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 /spl mu/m and a receiving pad size of 50 /spl mu/m, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture as it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology.