Showing papers on "Electronic packaging published in 2008"

High-Performance Flexible Hybrid Field-Effect Transistors Based on Cellulose Fiber Paper

Abstract: In this letter, we report for the first time the use of a sheet of cellulose-fiber-based paper as the dielectric layer used in oxide-based semiconductor thin-film field-effect transistors (FETs). In this new approach, we are using the cellulose-fiber-based paper in an ldquointerstraterdquo structure since the device is built on both sides of the cellulose sheet. Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility,(> 30 cm2 / vs drain-source current on/off modulation ratio of approximately 104, near-zero threshold voltage, enhancement n-type operation, and subthreshold gate voltage swing of 0.8 V/decade. The cellulose-fiber-based paper FETs' characteristics have been measured in air ambient conditions and present good stability, after two months of being processed. The obtained results outpace those of amorphous Si thin-film transistors (TFTs) and rival with the same oxide-based TFTs produced on either glass or crystalline silicon substrates. The compatibility of these devices with large-scale/large-area deposition techniques and low-cost substrates as well as their very low operating bias delineates this as a promising approach to attain high-performance disposable electronics like paper displays, smart labels, smart packaging, RFID, and point-of-care systems for self-analysis in bioapplications, among others.

A review of the influencing factors on anisotropic conductive adhesives joining technology in electrical applications

Abstract: New interconnect materials are always necessary as a result of evolving packaging technologies and increasing performance and environmental demands on electronic systems. Polymer-based conductive-adhesive materials have become widely used in many electronic packaging interconnect applications. Among all the conductive-adhesive materials, the anisotropic conductive adhesives (ACA) (or anisotropic conductive adhesive films, ACF) have gained popularity as a potential replacement for solder interconnects. The interest in using ACA instead of solder comes partly from the fact that the use of ACA for the direct interconnection of flipped silicon chips to printed circuits (flip chip packaging) offers numerous advantages such as reduced thickness, improved environmental compatibility, lowered assembly process temperature, increased metallization options, reduced cost, and decreased equipment needs. In this review, a summary of our understanding of the electrical, physical, thermal, chemical, environmental, and cost behaviors of ACA in conjunction with various packaging applications is elaborated. First, the formulation and curing kinetics of ACA materials, as well as the conduction mechanisms of ACA joints, are introduced; second, the influencing factors, including the boding process (boding temperature, boding pressure, curing conditions, reflow and misalignment processes, etc), the environmental factors (temperature, humidity, impact load, etc), and the properties of the components (the properties of the ACA, substrates, conductive particles, the bump height, etc), on the reliability of ACA joining technology are presented. Finally, future research areas and remaining issues are pointed out. The purpose is simply to pinpoint the most important papers that have played significant role for the advancement of the ACA bonding technology.

Review Of Recent Advances In Electrically Conductive Adhesive Materials And Technologies In Electronic Packaging

Abstract: Electrically Conductive Adhesives (ICAs: Isotropic Conductive Adhesives; ACAs: An-isotropic Conductive Adhesives; and NCAs: Non-conductive Adhesives) offer promising material solutions for fine pitch interconnects, low cost, low-temperature process and environmentally clean approaches in the electronic packaging technology. ICAs have been developed and used widely for traditional solder replacement, especially in surface mount devices and flip chip application. These also need to be lower cost with higher electrical/mechanical and reliability performances. ACAs have been widely used in flat panel display modules for high resolution, lightweight, thin profile and low power consumption in film forms (Anisotropic Conductive Films: ACFs) for last decades. Multi-layered ACF structures such as double and triple-layered ACFs were developed to meet fine pitch interconnection, low-temperature curing and strong adhesion requirements. Also, ACAs have been attracting much attention for their simple and lead-free proc...

Through silicon via copper electrodeposition for 3D integration

Abstract: Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.

Through-silicon via and die stacking technologies for microsystems-integration

Abstract: The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies A key challenge is however to perform such stacking in a cost-effective manner In this paper, a novel 3D TSV and 3D stacking technologies will be presented Application examples are MEMS packaging and heterogeneous integration of imaging devices

Trends of Power Electronic Packaging and Modeling

Abstract: A review of recent advances in power electronic packaging is presented based on the development of power device integration. The presentation will cover in more detail how advances in both semiconductor content and power advanced package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, the role of modeling is key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging

Abstract: Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays (BGAs) has been presented. Component types examined include-flex-substrate and rigid substrate BGAs. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of five million samples per second. High-speed video at 150000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree BGAs.

From Packaging to "Un"-Packaging - Trends in Power Semiconductor Modules

Abstract: Power semiconductor modules play a key role in power electronic systems. Their inherent advantage of integrating different power chips, circuits and sense, drive and protection functions into one sub-system with electrically insulated cooling has lead to a wide range of products, being different in size, power and function. This paper will provide an overview of today's power modules and packaging and interconnect technologies. Trends towards next generations of power modules will be highlighted. In the growing market of hybrid and electrical vehicles, products are emerging where power modules are "un-packaged" to arrive at highly integrated, compact sub-systems which are better suited for the harsh environmental conditions and the required power density than the classical power modules.

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

Abstract: A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.

Toward the Next Level of PCB Usage in Power Electronic Converters

Abstract: A means for power electronics to exploit the level of 3-D packaging already being implemented in compact consumer products, such as digital cameras, is investigated in order to increase its power density. The increase in functionality and usage of printed circuit board (PCB) in power electronic converters is highlighted and improvements proposed to boost PCB usage to the next level. The material and manufacturing cost of an embedded planar transformer in a PCB-assembled power converter has been substantially reduced by introducing flexible-foil PCB to create the many windings without increasing the remaining number of (expensive) rigid PCB layers. Aspects such as the required folding pattern and its PCB material usage receive qualitative and quantitative attention. Furthermore, increasing of PCB functionality as regards integration of passives, geometrical packaging, and 3-D thermal management enhancement has been addressed. Not only is it shown that the integration of passives into a single, multifunctional PCB transformer structure is feasible but also that the same integral PCB can be used to geometrically package the remaining bulky, low-frequency, discrete components to create a power-dense converter and enhance the 3-D thermal management. A power density improvement of 66% (from 150 to 250 W/L) is achieved by the technology demonstrator.

Thermal Management Technologies for Electronic Packaging: Current Capabilities and Future Challenges for Modelling Tools

Abstract: Extracting heat from electronic systems has always been a challenging task for electronic package designers. Ever increasing miniaturisation and functionality of Microsystems packaging technologies is resulting in increased power densities that current thermal management techniques are finding difficult to manage. Thermal management of electronics is a significant issue because of increasing volumetric power densities and the harsh environments in which they are deployed. Environmental factors are forcing companies to broaden their view of thermal management as energy management, where industry is being driven to minimise the amount of energy required to keep electronic systems cool. This paper will discuss both current capabilities and future requirements for passive and active cooling technologies. Modelling technologies which can be used by designers to predict optimal thermal/energy management solutions will also be discussed.

Design Envelopes and Optical Feature Extraction Techniques for Survivability of SnAg Lead-free Packaging Architectures Under Shock and Vibration

Abstract: In this paper, a design-envelope approach based on optical feature extraction techniques has been investigated for drop and shock survivability of electronic packaging has been presented for 6-leadfree solder alloy systems. Solder alloy systems investigated include, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu0.1Bi, Sn0.2Ag0.7Cu0.1Bi- 0.1Ni, 96.5Sn3.5Ag. Previously, digital image correlation (DIC) has been used for measurement of thermally-induced deformation and material-characterization. In this paper, DIC has been used for transient dynamic measurements, and optical feature extraction. Board assemblies have been subjected to shock-impact in various orientations including the JEDEC zero-degree drop and the vertical free-drop. Transient deformation has been measured using both digital image correlation and the strain gages. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include-flex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The potential of damage identification and tracking for various solder alloys has been investigated. Data on identification of damage proxies for competing failure mechanisms at the copper-to-solder, solder-to-printed circuit board, and copper-to-package substrate has been presented. Design envelopes have been developed based on statistical pattern recognition. The design-envelope is intended for component integration to ensure survivability in shock and vibration environments at a user-specified confidence level.

Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies

Abstract: The miniaturisation 3D integration/stacking systems has a significant impact on both thermal resistance and thermo-mechanical reliability. The trends regarding these issues are summarised for the different 3D integration approaches: 3D-SIP, 3D-WLP and 3D-SIC.

Active Electronic Media Device Packaging

Abstract: Active packaging for supplying power, data, or both power and data to an electronic media device while the device is housed within the active packaging is provided. The active packaging may include one or more electrical traces in-molded or printed onto the packaging that couple to a suitable connector on the device. Power may also be provided via one or more wireless power techniques. Multiple active packages may be conductively stacked to transmit power, data, or both power and data to a row or stack or devices. POM sensors integrated with or attached to the device (or the active packaging itself) may detect various movement events. Coordinated and synchronized display effects may be presented while the devices are housed within the active packaging.

Advanced Packaging: The Redistributed Chip Package

Abstract: The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Investigations of carbon nanotubes epoxy composites for electronics packaging

Abstract: The part of electronics packaging is steadily forced to adapt the requirements of the microelectronic industry. For future electronics application such needs will be: 1) steady miniaturisation of the electronic devices 2) high pin count up to 5000 i / o per device 3) pitches down to 20 mum 4) higher current density per devices 5) higher thermal dissipation loss This is only a small extract of the challenges facing the electronics packaging industry in the future. The aim and duty for electronics packaging is to realize a reliable package for future electronics. Commonplace materials for joining elements like solder are not able to solve these requirements. For example in [1] the authors describe that future IC's operating at high frequencies of 10-28 GHz, signal bandwidths of 20 Gbps and lower supply voltages require an estimated maximum of R (< 10 mOhm), L (<5-10pH) and C (<5-10 fF).[l] Current joining elements can not meet these requirements. To solve these problems the electronics packaging industry researches technologies and materials of the nanotechnology. Especially researches concerning new materials for electronics packaging rise up since the last three years. One of the most researched new materials are Carbon Nanotubes (CNT). Carbon Nanotubes have superior mechanical, electrical and thermal properties. Due to these properties CNT are considered as promising candidates in packaging technology. The most interesting field of application is the use of the Carbon Nanotubes as filler in electrical conductive adhesives. The aim is to improve the performance of conductive adhesives in comparison to common products. This study deals with characterization of carbon nanotube / epoxy adhesives in electronics packaging. For this study we optimize the CNT - adhesive system by modification of the CNT, use of different dispersion technologies and under variation of the epoxy matrix. The resulting adhesives are characterized by measuring their viscosity, mechanical strength and their thermal and electrical conductivity. For all studies Multi Wall Nanotubes were used which can be purchased at a reasonable price. For modification of the CNT they can be treated by low pressure plasma (cvd), UV / ozone treatment or modifiedchemically in solution to achieve a higher polarity resulting in a better dispersibility. Also bonding to the polymer matrix is improved. Success of the processes is studied by XPS and REM. For dispersion technology ultrasonic bath, speed mixing and/or treatment with a roll calander can be used. The polymer matrix is also varied in order to achieve an appropriate viscosity at the CNT-content of interest that enables good results in screen printing. Also CNT-polymer interaction can be adapted by varying polarity of the resin used. The distribution of CNT in the matrix is studied by TEM. The first investigations show that ultrasonic finger is the favourable dispersion technology to achieve well dispersed CNT. For modification of the CNT the plasma treatment came out to be efficient to give appropriate amounts of hydroxyl groups.

40-Gb/s Package Design Using Wire-Bonded Plastic Ball Grid Array

Abstract: A 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed was beyond the reach of conventional package designs, a new design methodology was proposed-discontinuity cancellation in both signal-current and return-current paths. The 3-D structures of bonding wires, vias, solder ball pads, and power distribution networks were optimized for the discontinuity cancellation. Two versions of four-layer WB-PBGA packages were designed; one according to the proposed methodology and the other conventionally. The proposed design methodology was verified with full-wave simulation, passive bandwidth measurement, time domain reflectometry (TDR), eye diagram measurement, and jitter analysis.

Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Broadband BGA-Via Transitions for Reliable RF/Microwave LTCC-SiP Module Packaging

Abstract: This letter presents two broadband ball grid array-via transition structures applicable in reliable radio frequency/microwave low-temperature co-fired ceramic system-in-package (LTCC-SiP) module packaging from dc up to the K-band. The first transition provides better electromagnetic shielding, while the second one exhibits 40% wider bandwidth by including an air-cavity in the LTCC module. To specifically address board-level reliability, novel plastic-core solder balls as large as 1100 mum were employed. The measured 1-dB cutoff frequencies of the transition structures, all the way from the printed circuit board up to the top surface of the module package, were 19 and 27 GHz. In addition, equivalent circuit models for the transitions were developed.

Advances in LED packaging and thermal management materials

Abstract: Heat dissipation, thermal stresses and cost are key light-emitting diode (LED) packaging issues. Heat dissipation limits power levels. Thermal stresses affect performance and reliability. Copper, aluminum and conventional polymeric printed circuit boards (PCBs) have high coefficients of thermal expansion, which can cause high thermal stresses. Most traditional low-coefficient-of-thermal-expansion (CTE) materials like tungsten/copper, which date from the mid 20th century, have thermal conductivities that are no better than those of aluminum alloys, about 200 W/m-K. An OIDA LED workshop cited a need for better thermal materials. There are an increasing number of low-CTE materials with thermal conductivities ranging between that of copper (400 W/m-K) and 1700 W/m-K, and many other low-CTE materials with lower thermal conductivities. Some of these materials are low cost. Others have the potential to be low cost in high-volume production. High-thermal-conductivity materials enable higher power levels, potentially reducing the number of required LEDs. Advanced thermal materials can constrain PCB CTE and greatly increase thermal conductivity. This paper reviews traditional packaging materials and advanced thermal management materials. The latter provide the packaging engineer with a greater range of options than in the past. Topics include properties, status, applications, cost, using advanced materials to fix manufacturing problems, and future directions, including composites reinforced with carbon nanotubes and other thermally conductive materials.

Copper electrodeposition for 3D integration

Abstract: Two dimensional (2D) integration has been the traditional approach for IC integration. Increasing demands for providing electronic devices with superior performance and functionality in more efficient and compact packages has driven the semiconductor industry to develop more advanced packaging technologies.

Fatigue and fracture assessment for reliability in electronics packaging

Abstract: Modern electronics products relentlessly become more complex, higher in density and speed, and thinner and lighter for greater portability. The package of these products is therefore critical. The reliability of the interconnection of electronics packaging has become a critical issue. In this study, the novel testing methods for electronic packaging are introduced and failure mechanisms of electronic packaging are explained. Electronics packaging is subjected to mechanical vibration and thermal cyclic loads which lead to fatigue crack initiation, propagation and the ultimate fracture of the packaging. A small-sized electromagnetic-type bending cycling tester, a micro-mechanical testing machine, and thermal fatigue testing apparatus were specially developed for the reliability assessment of electronics packaging. The long-term reliability of an electronic component under cyclic bending induced high-cycle fatigue was assessed. The high-cycle bending-fatigue test was performed using an electromagnetic-type testing machine. The time to failure was determined by measuring the changes in resistance. Using the micro-mechanical tester, low cycle fatigues were performed and compared with the results of a finite element analysis to investigate the optimal shape of solder bumps in electronic packaging. Fatigue tests on various lead-free solder materials are discussed. To assess the resistance against thermal loads, pseudo-power cycling method is developed. Thermal fatigue tests of lead-containing and lead-free solder joints of electronic packaging were performed using the pseudo-power cycling tester. The results from the thermal fatigue tests are compared with the mechanical fatigue data in terms of the inelastic energy dissipation per cycle. It was found that the mechanical load has a longer fatigue life than the thermal load at the same inelastic energy dissipation per cycle.

Resonator miniaturization for oscillators

Abstract: This paper first compares the trends and the challenges of miniaturization for silicon micro-electromechanical system (MEMS) resonators and quartz crystals. Core resonators are compared in terms of electrical parameters, frequency definitions and tolerances, temperature compensation. As packaging occupies much larger area than core resonators, miniaturization of packaging is also discussed.

Integration of high aspect ratio tapered silicon via for through-silicon interconnection

Abstract: This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a 3-step approach has been developed and characterized which controls via depth, sidewall profile and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

Tri-Layer Structures Subjected to Combined Temperature and Mechanical Loadings

Abstract: Thermal stress has been a concern in electronic packaging for decades. More recently, mechanical bending of printed circuit board (PCB) assembly has attracted increased interest due to the drop impact failure of interconnects in mobile products. Analytical solutions are available in the literatures for a PCB assembly modeled as a tri-layer structure, consisting of IC components, PCBs, and an interconnect layer, subjected to either thermal stress or mechanical bending, but there are no known reports for combined loadings. This paper presents a comprehensive treatment for a PCB assembly subjected to combined temperature and mechanical loadings, taking into account the axial, shear, and flexural deformation of the interconnects. Solutions are provided for two types of interconnect layer: one in which the interconnect layer is made of a continuous element such as adhesive, and another in which the interconnect layer is made of discrete elements such as solder joints. The solutions were successfully validated with finite-element analysis, and design analyses were performed for both types of interconnect layers.

Heat Sink Material Selection in Electronic Devices by Computational Approach

Abstract: Due to the increasing complexity, miniaturization and higher density of components in modern devices, reliability and lifetime are important issues in electronic packaging. In modern electronic devices, the packaged structure consists of a variety of metallic, ceramic, plastic or composites components. The large differences in coefficient of thermal expansion (CTE) between ceramic substrates (such as Al2O3 and AlN) heat dissipation materials (such as Cu and Al,) and semiconductors (such as Si and GaAs) induce thermal stress and therefore possible thermal failure in solder joints or ceramic substrates. As a result, to ensure the reliability of electronic devices at increased packing and power densities, thermal management must be considered as a critical aspect in the design of multi-chip modules. There is, therefore, a strong need for the development of new designs utilising novel heat dissipation materials with low coefficients of thermal expansion and high thermal conductivities. During the last decade, the developments in material selection and thermo-mechanical modelling software have lead to design optimisation of complex devices and the prediction of their lifetime.[1,2] It is very important to study material and design parameters that would improve reliability. The challenge is determining the thermal properties of new materials such as composites, which can be very powerful materials in controlling thermal stress and, as a result, increasing the reliability of electronic packages. In this paper, thermo-mechanical modelling predicts i) stress/strain responses in the electronic device under thermal loads, and ii) the corresponding reliability (lifetime). The thermal stress and strain analyses in this study have been performed with FEMLAB multi-physics software. Furthermore, it models the couple between different materials in complex device designs.

Reliability of Anisotropic Conductive Adhesive Joints in Electronic Packaging Applications

Abstract: New interconnection materials are always necessary as a result of evolving packaging technologies and increasing performance and environmental demands on electronic systems. In particular, anisotropic conductive adhesives (ACAs) have gained popularity as a potential replacement for solder interconnects. Despite numerous benefits, ACA-type packages pose several reliability problems. During the last 10 years, tremendous research and development efforts have been spent on improving the reliability of ACA joints. In this paper, the effects of the bonding process (including the bonding temperature, bonding pressure, curing conditions and reflow processes) on the reliability of ACA joints are presented. Then the effects of the environmental factors (including high temperature, humidity, thermal cycling, impact load, etc.) on the reliability of ACA joints are discussed. Finally, the effects of the properties of the components (including properties of substrates, ACAs, conductive particles and the bump height) on...

Laser based fast prototyping methodology of producing stretchable and conformable electronic systems

Abstract: For user comfort and reliability reasons, electronic circuits for human body related applications should ideally be soft, elastic and stretchable, for smart textile application, but also for applications which need a high level of biocompatibility. We are developing several roll-to roll technologies using MID (Molded Interconnect Device) and low cost standard PCB technology (Printed Circuit Board) to produce soft, stretchable, human-compatible packaging. All those technologies are based on a sacrificial layer on where meander shaped interconnections are patterned. Those stretchable interconnections are connecting together non-stretchable functional islands on where SMD components are soldered. All the system is then embedded in stretchable polymer matrix, silicone rubber or polyurethane. All these technologies are using standards methodologies for PCB productions (lamination, photolithography, copper etching, reflow oven lead free soldering). A fast prototyping technology has been developed to ease the development of stretchable electronic circuits. Less than 1 day is necessary from CAD design to finalization: Rigid or flexible standard components or electronic sub-systems are interconnected with YAG laser shaped meander interconnections and molded in silicone rubber afterwards. From any kind of flexible circuit, stretchable circuit can be produced using this methodology. The stretchable meander interconnection can be stretched more than 100% and can sustain at least 3000 cycles at 20% of deformation. This paper presents a general overview of stretchable electronic process, a detailed view of the fast prototyping technology using YAG laser cutting, and the demonstrators developed in the frame of the European project STELLA (Stretchable Electronic for large area) [7] and in the Belgian project SWEET (Stretchable and washable electronic in textile) [8] and BIOFLEX (Biocompatible stretchable electronic system) [9].