Showing papers on "Electronic packaging published in 2012"

Printing conformal electronics on 3D structures with Aerosol Jet technology

Abstract: Fabrication of 3D mechanical structures is sometimes achieved by layer-wise printing of inks and resins in conjunction with treatments such as photonic curing and laser sintering. The non-treated material is typically dissolved leaving the final 3D part. Such techniques are generally limited to a single material which makes it difficult to integrate high resolution, conformal electronics over part surfaces. In this paper, we demonstrate a novel, non-contact technique for printing conformal circuits called Aerosol Jet printing. This technique creates a collimated jet of aerosol droplets that extend 2–5 mm from the nozzle to the target. The deposited features can be as small as 10 microns or as large as a centimeter wide. A variety of materials can be printed such as metal nanoparticle inks, polymers, adhesives, ceramics, and bio-active matter. The print head direction and XYZ positioning is controlled by CAD/CAM software which allows conformal printing onto 3D substrates having a high level of surface topography. For example, metallic traces can be printed into 3D shapes such as trenches and via holes, as well as onto sidewalls and convex and concave surfaces. We discuss the fabrication of a conformal phase array antenna, embedded circuitry and sensors, and electronic packaging.

System Integration of Electronic Functions in Smart Packaging Applications

Abstract: A system integration scheme relevant for smart packaging applications is presented. Recent advances in printed electronics, radio frequency identification tag production, and standardization of communication protocols are factors that increase the design freedom for new applications. As in all new technology fields, the first products are expected to appear in the high-cost segment attracting early adopters in the form of niche products. A reasonable assumption is that these products will come from hybridization of different types of technologies. Such a scenario is likely since no technology solution available can provide all features that these types of applications demand. There is a need of standard solutions for hybridization of silicon devices and printed (or foil-type) components. Conductive ink technology is a powerful tool for hybridization and customization of large-area electronics, providing 3-D integration and large-area customization. However, high-performance communication and advanced processing demand the use of silicon. Smart hybridization solutions allow combination of the best from both worlds. This paper analyzes the requirements on hybridization technologies suitable for smart packaging applications and provides design examples on integration of intrusion surveillance solutions for cellulose-based packaging applications. It shows that even though the current hybridization technologies are far from optimal, they can provide a considerable design freedom and system performance.

New assembly and interconnect technologies for power modules

Abstract: Higher operation temperatures and the current density increase of new IGBT generations make it more and more complicated to meet the quality requirements for power electronic modules. Especially the increasing heat dissipation inside the silicon leads to maximum operation temperatures of nearly 200 deg C. As a result new packaging technologies are needed to face the demands of power modules in the future. In case of the chip-to-substrate interconnect basically two technology trends for an improved die attach procedure became visible. On the one hand diffusion bonding has been presented, where the joint is formed from high melting intermetallics. On the other hand the chip-to-substrate interconnect can be realized by sintering silver particles, resulting in a monometallic porous die attach layer. This paper presents a comparison of these two technology trends with respect to their applicability for power electronics packaging.

A review of stencil printing for microelectronic packaging

Abstract: Purpose – The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.Design/methodology/approach – This paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.Findings – This article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.Originality/value – Stencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and ...

Bond pad for wafer and package for cmos imager

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Advanced Thermal Management Materials

Abstract: Introduction to Thermal Management in Microelectronics Packaging.- Requirements of Thermal Management Materials.- Overview of Traditional Thermal Management Materials.-Development of Advanced Thermal Management Materials.- Properties of WCu, MoCu, Cu/MoCu/Cu High Performance Heat Sink Materials and Manufacturing Technologies.- Novel Methods for Manufacturing of W85-Cu Heat Sinks for Electronic Packaging Applications.- Improved Manufacturing Process of Cu/Mo70-Cu/Cu Composite Heat Sinks for Electronic Packaging Applications.- Al/SiC Thermal Management Materials.- Understanding of Laser, Laser diodes, Laser diode packaging and its relationship to Tungsten Copper.- Future Trend of Advanced Thermal Management Materials.

Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure

Abstract: A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. The power switches in a popular phase leg electrical topology are orientated in a face up/face down configuration. Large bonding areas between dies and substrates combined with a compact busbar interface allow this packaging technology to offer dramatic improvements in electrical conversion efficiency and electromagnetic interference containment.

Transient Frequency-Domain Thermal Measurements With Applications to Electronic Packaging

Abstract: Non-uniform power distribution, increased die-size, and multiple-chip modules present new challenges for the thermal management of modern integrated circuit (IC) packages. Thermal characterization techniques capable of resolving partial thermal resistances at the component level have received increased emphasis in development of advanced packaging technologies. This paper aims to develop a practical method for thermal characterization of IC packages using the frequency-domain measurement technique as a complementary technique to the widely used time-domain thermal transient measurement technique. This paper discusses practical implementation of the technique and demonstrates both thermal modeling and experimental results. Thermal impedances measured in frequency-domain yield the structure function, which describes the dynamic thermal response of the device based on thermal RC network analysis. Various applications of this technique in thermal characterization of the IC packages subjected to field conditions are also discussed.

Reduced-Size Low-Voltage RF MEMS X-Band Phase Shifter Integrated on Multilayer Organic Package

Abstract: This paper presents an X-band two-bit phase shifter that integrates single-pole four-throw (SP4T) piezoelectric microelectromechanical switches with a compact 3-D passive design on a liquid crystal polymer (LCP) organic substrate. The multilayer LCP process allows a low-cost and lightweight circuit that can easily be integrated with other radio frequency front-end components, such as an antenna, at the packaging level. By routing lines onto embedded multilayers, a 22.5% reduction in area is achieved. In addition, low-loss piezoelectric SP4T switches with a 7 V actuation voltage are used to switch between different phase delays. The phase shifter exhibits a loss of 0.75 dB/bit with 2.25° average phase error at 10 GHz.

System Integration by Advanced Electronics Packaging

Abstract: This chapter presents a review of the status and the trends of system integration by electronics packaging. At first an analysis of the system drivers will be given and the requirements for System in Package (SiP), followed up by More-than-Moore approaches leading to Hetero-System-Integration. One focus of this chapter will lie on the three-dimensional (3D) integration in electronic packages, their assembly and interconnection technologies. This type of system integration has significant advantages for higher density of functions, smaller sizes and higher clock rates. A second focus of this chapter is directed towards challenges for materials of advanced electronics packaging.

FET arrays as CPI sensors for 3D stacking and packaging characterization

Abstract: FET arrays are investigated from the viewpoint of Chip-Package Interaction (CPI) sensor suitability and presented as a possible solution for experimental characterization of CPI effects during 3D assembly steps: Stacking and packaging. The study presents a methodology consisting of an experimental approach with the support of FEM modeling. The use of the transistors as stress sensors covering in-plane stress components is justified, after which the applicability of the transistors to the actual stacking and packaging stress states is discussed. Calibration to in-plane stress of long and short channel transistors, p and n type, is performed to obtain sensor sensitivities and link stress to current shift by according calculated piezocoefficients. Testing the FET arrays as sensors is firstly done by means of a simple structure where a die is glued to a plastic substrate. The electrical measurements are compared to FEM models and profilometric scans. The sensors are next utilized to obtain first results from 3D stacking and packaging. The underfill - microbump mechanism in a 2-die stack is quantified and initial results on overmould impact are discussed.

Advanced mixed-mode bending test: A rapid, inexpensive and accurate method for fracture-mechanical interface characterisation

Abstract: This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximummode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut fromreal devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for delamination testing in electronic packaging.

Graphene heat spreader for thermal management of hot spots in electronic packaging

Abstract: Monolayer graphene was fabricated using thermal CVD for the application of heat spreader in electronic packaging. Platinum (Pt) micro-heater embedded thermal testing chips were utilized to evaluate the thermal performance of the graphene heat spreader. The hot spot temperature was decreased by about 5 °C at a heat flux of up to 800W/cm2. It is possible to further improve the thermal performance of graphene heat spreader by optimizing the synthesis parameters and transfer process.

Research progress of high aluminum-silicon alloys in electronic packaging

Abstract: Basic requirements of electronic packaging materials were reviewed,the characteristics and research situation of the high aluminum-silicon alloys were discussed,and the advantages and disadvantages of the preparation processes that include casting,infiltration,rapid solidification powder metallurgy and spray-forming were analyzed.Moreover,the development tendency of high aluminum-silicon alloy electronic packaging materials was pointed out.

RF-MEMS switch module in a 0.25 μm BiCMOS technology

Abstract: A BiCMOS embedded RF-MEMS switch module is demonstrated. The module consists of four main blocks: 1) RF-MEMS switch technology, 2) Switch models for design-kit implementation, 3) High Voltage (HV) generation and digital interface, 4) Flexible packaging. The RF-MEMS switch technology is detailed by focusing on the contact model, especially in the down-state. Electromagnetic (EM) and lumped-element models are demonstrated to integrate into foundry process design kit (PDK). The integrated on-chip HV generation and control circuitries are described. A flexible packaging technique is also introduced to package either standalone switches or circuits with several switches.

Thermally Conductive Polymer Composites for Electronic Packaging Applications

Abstract: Advancements in the semiconductor industry have lead to the miniaturization of components and increased power densities, resulting in thermal management issues In response to this shift, finding multifunctional materials with excellent thermal conductivity and tailored electrical properties are becoming increasingly important For this research thesis, three different studies were conducted to develop and characterize thermally conductive polymer composites In the first study, a PPS matrix was combined with different types of carbon-based fillers to determine the effects of filler’s size, shape, and orientation on thermal conductivity In the second study, effects of adding ceramic- and carbon- based fillers on the tailored thermal and electrical properties of composites were investigated Lastly, the possibility of improving the thermal conductivity by introducing and aligning polymer fibers in the composites was investigated The composites were characterized with respect to their physical, thermal, and electrical properties to propose possibilities of application in the electronic packaging industries

Corrosion Resistance of Pb-Free and Novel Nano-Composite Solders in Electronic Packaging

Abstract: Tin-lead (Sn-Pb) alloys for metal interconnections were first used about 2000 years ago. Recently, the use of alloys has become essential for the interconnection and packaging of virtually all electronic products and circuits. Sn-Pb solder alloys have been widely used in the modern electronics industry because of their low melting points, good wettability, good corrosion resistance, low cost, reasonable electrical conductivity, and satisfactory mechanical properties. However, due to health concerns, recent legislation, and market pressures [1], the electronic industry is moving toward green manufacturing as a global trend. In the area of packaging, mainly driven by European RoHS (Reduction of Hazardous Substances), lead was banned effective July 1, 2006, except in some exempt items. In addition, Pb and Pb-containing compounds, as cited by the Environmental Protection Agency (EPA) of the US, are listed among the top 17 chemicals posing the greatest threat to human life and the environment [2] because of lead's toxicity [3]. In the electronics industry, the lead generated by the disposal of electronic assemblies is considered hazardous to the environment. Therefore, developing viable alternative Pb-free solders for electronic assemblies is of principal importance.

Application of the Spark Plasma Sintering Technique to Low-Temperature Copper Bonding

Abstract: Planar structures, in which a power die is soldered on a substrate and wirebonds are used to connect the top of the die with the substrate, are limited in terms of thermal management and power density. 3-D packaging techniques have been proposed to overcome these limits. Here, an innovative copper-to-copper bonding solution is presented, that can be used for 3-D packaging. The bonding process is described and the effect of the bonding parameters is investigated. It is found that this technique is compatible with the requirements of power electronic packaging. A test assembly including a silicon power die and ceramic substrates is presented.

Advanced mixed-mode bending test: A rapid, inexpensive and accurate method for fracture-mechanical interface characterisation

Abstract: This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximum mode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut from real devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for delamination testing in electronic packaging.

Applications of multi-walled carbon nanotube in electronic packaging

Abstract: Thermal management of integrated circuit chip is an increasing important challenge faced today. Heat dissipation of the chip is generally achieved through the die attach material and solders. With the temperature gradients in these materials, high thermo-mechanical stress will be developed in them, and thus they must also be mechanically strong so as to provide a good mechanical support to the chip. The use of multi-walled carbon nanotube to enhance the thermal conductivity, and the mechanical strength of die attach epoxy and Pb-free solder is demonstrated in this work.

Solder joints properties as function of multiple reflow Vapor Phase Soldering process

Abstract: The continuous trend towards high density and miniaturization of electronic devices involves the use of multiple reflow processes in assembling technologies for second level of interconnections in electronic packaging hierarchy. According to the “4P” Soldering Model concept (4PSMC), considering the Pad-Paste-Pin-Process elements as Key Process Input Variables (KPIV), the solder joints are the result of KPIV synergistically interactions and correlations with consequences over their microstructure. In the paper, taking into consideration the cooling rate influence over intermetallic compounds (IMC) formation and microstructure, there was described the investigations over electrical and mechanical properties of solder joints resulted from multiple reflow Vapor Phase Soldering (VPS) process, in terms of 4PSMC. Maintaining the pad, pin and paste of KPIV as references measurements of solder joints resistances and shear forces were perform as function of VPS process's number for two values of cooling rate, respectively IMC microstructures and stereofractography studies. The results of the studies performed and presented in the paper will be use for improving process control in order to assure the solder joints reliability, to minimize losses on VPS lines, to reduce defects number and rework time.

Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultrathin Device

Abstract: Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this paper, piezoresistive stress sensors were used to evaluate the stresses in device wafer after wafer bumping process, such as under bump metallization fabrication, dry-film process, and solder bumping. For the stress evaluation, n-type piezoresistive stress sensors were fabricated on p-type (100) silicon wafer and then sensors were calibrated to determine piezoresistive coefficients. The calibrated sensor wafers were finally used to measure residual in-plane stresses at the surface of device wafer. Due to the growing demand of portable and handheld devices, the reliability of electronic packages with Pb-free solder under drop impact condition has become an issue of concern. This paper aims to measure the real-time stress in an ultrathin die during a drop test to ascertain whether die cracking is a possible problem when dealing with 50-μm-thick dies. The advantages of these stress data are that they: 1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and 2) are important to enhance survivability during wafer bumping, handling and packaging.

Process for preparing Si-Al alloy electronic packaging material by spray deposition

Abstract: The invention relates to a process for preparing a Si-Al alloy electronic packaging material by spray deposition. The process comprises the following steps of: preparing the Si-Al alloy electronic packaging material by a spray deposition process, wherein the alloy comprises 40 to 60 percent of Si and the balance of Al; and machining to remove skin and an end face from a billet subjected to spray deposition, slicing the Si-Al alloy billet by a linear cutting process, compacting Si-Al alloy slices by a hot isostatic pressing process, maintaining pressure at the temperature of between 500 and 550 DEG C under the pressure of 100 to 150MPa for 0.5 to 3 hours, and thus obtaining the electronic packaging material with the thermal expansion coefficient of 8 to 13ppm/K, the tensile strength of 150 to 300MPa and the density of 2.3 to 2.6g/cm . The Si-Al electronic packaging material prepared by the process does not contain any harmful element, is environment-friendly, is easy to cure, and is suitable for industrial production.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Abstract: In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Quality assurance for wire connections used in integrated circuits via magnetic imaging

Abstract: Electronic components used in high power applications must be able to deal with rough operating conditions, like frequent changes of temperature, mechanical stress and short-term electrical overload. An important factor in this context is the electronic packaging, especially the electrical interconnection between the die and the output pins. In order to evaluate the effects of thermo-mechanical stress on the electrical interconnections during the lifetime (which can be up to 25 years), a simulation using the finite-element method is the mainly used approach. Another possibility is to simulate stress cycles through applying an equivalent mechanical or electrical load with regards to the expected operating conditions. To evaluate the results of the stress simulation on the electrical interconnections, the chip package must be cut open and this implies mechanical stress. This paper presents a preliminary investigation for a non destructive evaluation of electrical interconnections in integrated circuits via magnetic imaging.

Vias-last process technology for thick 2.5D Si interposers

Abstract: Relative to traditional chip-to-substrate or chip-to-PCB packaging, solutions utilizing 2.5D silicon interposers can provide significantly higher I/O densities, resulting in reduced size, lower power consumption, and higher functionality [1,2]. One example of an advanced packaging application enabled by Si interposers is an embedded computing module (ECM) illustrated in Figure 1. Benefits of this advanced electronic packaging approach include (1) reduction in size by a factor of 2–3, (2) reduction in system power, and (3) elimination of on-die termination resistors [3].

Transient thermal analysis as failure analytical tool in electronic packaging

Abstract: New packaging technologies are necessary to meet the demand for smaller and more reliable electronic devices. The so-called system-in-package (SiP) concept brings different technologies, material combinations and processes together in one package. To ensure the reliability of such a package reliable, fast and non-destructive failure analysis are needed.

High-thermal conductivity electronic packaging material and preparation method thereof

Abstract: The invention belongs to the technical field of electronic packaging materials, and provides a high-thermal conductivity electronic packaging material and a preparation method thereof. The packaging material comprises a reinforcement body comprising diamond grains, pure copper powder and a third component, namely chromium, molybdenum, silicon, titanium or tungsten, wherein the volume percentage of the reinforcement body is 25 to 80 percent and that of the third component is 0.01 to 10 percent. The preparation method comprises the following steps: mixing the reinforcement body, the pure copperpowder and the third component evenly in proportion, and reducing the mixture by hydrogen in a reducing furnace for 1 to 5 hours, at a temperature between 200 and 400 DEG C; feeding the mixed powder in a graphite die and treating the mixed powder by adopting a spark plasma sintering process; vacuumizing the graphite die, heating up the graphite die to between 700 and 1,100 DEG C at a rate of temperature increase of 50 to 200 DEG C/min and pressurizing the graphite die to between 20 and 50MPa; and carrying out heat preservation for 1 to 20 minutes when reaching a sintering temperature and thentaking the packaging material out for demoulding after furnace cooling.

Die-level photolithography and etchless parylene packaging processes for on-CMOS electrochemical biosensors

Abstract: Integrated sensor arrays on CMOS instrumentation chips are attractive to many biological and biomedical sensor applications. However, the packaging of CMOS circuitry for use within a liquid environment remains as an open challenge. Reliable post-CMOS electrode fabrication and packaging processes that are critical to the development of integrated electrochemical biosensors are presented in this paper. A die-level photolithography process was developed that provides uniform coverage for accurate patterning over 87% of a 3×3mm2 silicon substrate. In addition, a new process has been developed to package post-CMOS fabricated electrode arrays. This etchless parylene packaging reduces processing time and improves fabrication yield. These techniques enable realization of on-CMOS biosensors operating in liquids.