Showing papers on "Electronic packaging published in 2015"

Robust Ag nanoplate ink for flexible electronics packaging

Abstract: Nanoinks are currently a topic of heightened interest with respect to low temperature bonding processes and printable electronics. We have developed an innovative polyvinylpyrrolidone (PVP)-stabilized Ag nanoplate ink amenable to very strong low temperature packaging, and investigated the relationship between bonding strength and electrical conductivity post-bonding. PVP shell plastic deformations observed in failure microcracks with the formation of PVP nanofibers, revealed bonding strength at low temperatures (<250 °C) was primarily due to adhesive bonding. It is found that, utilizing photonic sintering, ∼70 °C reduction of transformation temperature from adhesive to metallic bonding was achieved compared to that of thermal sintering. A numerical simulation was developed to better understand the influences of the light-induced heat generation, which demonstrated near-infrared light can facilitate sintering. Bonding strengths of 27 MPa were achieved at room temperatures, and 29.4 MPa at 210 °C with photonic sintering. Moreover, the anisotropic resistivity was observed with different thermal dependences. These results demonstrate Ag nanoplate inks have potential for low temperature 3D interconnections in lead-free microcircuits, flexible electronic packaging, and diverse sensing applications.

A novel monolithic piezoelectric actuated flexure-mechanism based wire clamp for microelectronic device packaging

Abstract: A novel monolithic piezoelectric actuated wire clamp is presented in this paper to achieve fast, accurate, and robust microelectronic device packaging. The wire clamp has compact, flexure-based mechanical structure and light weight. To obtain large and robust jaw displacements and ensure parallel jaw grasping, a two-stage amplification composed of a homothetic bridge type mechanism and a parallelogram leverage mechanism was designed. Pseudo-rigid-body model and Lagrange approaches were employed to conduct the kinematic, static, and dynamic modeling of the wire clamp and optimization design was carried out. The displacement amplification ratio, maximum allowable stress, and natural frequency were calculated. Finite element analysis (FEA) was conducted to evaluate the characteristics of the wire clamp and wire electro discharge machining technique was utilized to fabricate the monolithic structure. Experimental tests were carried out to investigate the performance and the experimental results match well with the theoretical calculation and FEA. The amplification ratio of the clamp is 20.96 and the working mode frequency is 895 Hz. Step response test shows that the wire clamp has fast response and high accuracy and the motion resolution is 0.2 μm. High speed precision grasping operations of gold and copper wires were realized using the wire clamper.

Optical and Electronic Packaging Processes for Silicon Photonic Systems

Abstract: Fiber optic interconnection processes and hybrid integration of electronic devices for high speed Si photonic systems are presented. Thermal effects arising from these hybrid integration processes are also investigated. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented. This includes the presentation of fundamental photonic packaging design rules which can greatly reduce the time and cost associated with the development of complex Si photonic devices.

Telescoping Solar Array Concept for Achieving High Packaging Efficiency

Abstract: Lightweight, high-efficiency solar arrays are required for future deep space missions using high-power Solar Electric Propulsion (SEP). Structural performance metrics for state-of-the art 30-50 kW flexible blanket arrays recently demonstrated in ground tests are approximately 40 kW/cu m packaging efficiency, 150 W/kg specific power, 0.1 Hz deployed stiffness, and 0.2 g deployed strength. Much larger arrays with up to a megawatt or more of power and improved packaging and specific power are of interest to mission planners for minimizing launch and life cycle costs of Mars exploration. A new concept referred to as the Compact Telescoping Array (CTA) with 60 kW/cu m packaging efficiency at 1 MW of power is described herein. Performance metrics as a function of array size and corresponding power level are derived analytically and validated by finite element analysis. Feasible CTA packaging and deployment approaches are also described. The CTA was developed, in part, to serve as a NASA reference solar array concept against which other proposed designs of 50-1000 kW arrays for future high-power SEP missions could be compared.

Pulse Electroplating of Ultrafine Grained Tin Coating

Abstract: In the electronic packaging industries, soldering materials are essential in joining various microelectronic networks. Solders assure the reliability of joints and protect the micro‐ electronic packaging devices. They provide electrical, thermal, and mechanical continuity among various interconnections in an electronic device. The service performance of all the electronic appliances depends on high strength and durable soldering materials. Lead-containing solders are in use for years, resulting in an extensive database for the re‐ liability of these materials. However, due to toxicity and legislations, lead-free solders are now being developed. As tin (Sn) is the major component of solders, this chapter presents the detailed results and discussion about the metallurgical overview of Sn, synthesis, and characterization of pulse electrodeposited pure tin finish from different aqueous solution baths. The experiments on pulse electrodeposition such as common tin plating baths em‐ ployed, their chemical compositions, rationale behind their selection and their characteri‐ zation by bath conductivity and cathodic current efficiency, microstructures, and tin whisker growth are discussed. Further, the effect of pulse electrodeposition parameters such as current density, additive concentration, pH, duty cycle, frequency, temperature, and stirring speed on microstructural characteristics of the coating obtained from sulfate bath and their effect on grain size distribution have been presented.

Thermal and dielectric behaviour of polypropylene composites reinforced with ceramic fillers

Abstract: This study aims at investigating the thermal and dielectric behaviour of thermoplastic polymer based packaging materials for microelectronics applications. Thermally conducting, but electrically insulating, polymer matrix composites that exhibit low value of coefficient of thermal expansion (CTE) are needed for electronic packaging. For developing such composites, two different ceramics i.e. micro-sized aluminium nitride and aluminium oxide (Al2O3) are reinforced in polypropylene individually. Compression moulding technique is used for fabrication purpose. Thermal properties like effective thermal conductivity (keff), glass transition temperature (Tg), CTE and electrical property like dielectric constant (ec) of composites are measured and reported. In addition, physical properties and morphological features are also studied. The experimental findings are interpreted using appropriate theoretical models. The results show that, while the incorporation of filler improves the keff and Tg, the CTE decreases favourably and also increase in dielectric constant is suitably controlled. It is found that the measured properties of the composites are suitable for certain applications like electronic packaging and printed circuit boards.

Electrostatic dissipative foams and process for the preparation thereof

Abstract: The present invention relates to the development of electrostatic dissipative (ESD) electronic packaging materials based on the electrically conducting nanofiller decorated polyurethane foams and also describes a process for the preparation of the same. More specifically it relates to the development of electrically conducting foams by providing a coating of 0.003 to 2.97 vol % loading of electrically conducting materials (like conducting polymers, functionalized carbon nanotubes, graphene analogues etc) over/onto otherwise electrically insulating surface of foams. The combination of low density, mechanical flexibility, resilience and surface conductivity collectively contribute towards their excellent shock absorption and static charge dissipation capabilities. In particular, these foams display surface resistivity value <109 ohm/sq and static charge dissipation time <0.5 sec, which clearly demonstrate their potential for electronic packaging applications. Besides, these foams could also be useful for antistatic dust filters, clean-room/medical apparels, static-free footwear, static dissipative upholstery items, antistatic/dissipative floorings/tiles etc.

Metal-based composite material enhanced by three-dimensional networked diamond framework as well as preparation method

Abstract: The invention provides a copper-based composite material enhanced by a three-dimensional networked diamond framework as well as a preparation method. The composite material comprises a metal base, the three-dimensional networked diamond framework and diamond particles, wherein the metal base is a common electronic packaging metal material such as Al, Cu, Ag and the like; the three-dimensional networked diamond framework adopts a substrate type or self-supporting type and is prepared by depositing diamond on the three-dimensional networked substrate which is machined and integrally formed or woven by one-dimensional wires; the three-dimensional networked diamond framework and the diamond particles all need surface modification treatment. According to the composite material, the three-dimensional networked diamond framework is distributed in the metal base, so that the composite material has excellent thermal conduction in the direction of the three-dimensional networked diamond framework, a series-parallel connection combined thermal conduction structure formed through addition of the diamond particles further improves the thermal conduction efficiency, and the composite material can be used as electronic packaging and heat sink materials and the like and solves the problem about packaging electronic devices with high temperature, high frequency and high power.

Microstructure and properties of Al/Sip composites for thermal management applications

Abstract: Aluminum matrix composite reinforced with high amount of Si particle is an advanced electronic packaging material used in thermal management. In this work, Al/Sip composites with different Si contents were prepared by rapid solidification and hot pressing. Fine and homogeneous microstructures with defect-free were achieved, and no detrimental reaction was detected. The typical thermo-physical properties such as the thermal conductivity and coefficient of thermal expansion (CTE) of the Al/Sip composites were acceptable as electronic packaging material for semiconductor devices. The CTE increased gradually with the temperature. Additionally, the mechanical properties of the composites were measured. The technological performance (workability, platability, and laser weldability) of the composites were also evaluated.

Electronic packaging of the IBM z13 processor drawer

Abstract: IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracraft D. Kaller G. Edlund T. Strach The electronic packaging of the IBM z13i is the foundation for a processor drawer that provides a significant increase in processing power relative to the IBM zEnterpriseA EC12 (zEC12) system while managing power and cost to meet the z13 product objectives. The z13 system architecture differs from previous high-end z Systemsi designs due to the introduction of a drawer-based processor design, organic single-chip modules (SCMs) in place of the ceramic MCMs (multi-chip modules), and a cabled interconnect between drawers in place of the PCB (printed circuit board) backplane of the zEC12. These innovations are coupled with next-generation signaling interfaces, providing a significant increase in signal bandwidth. The next-generation voltage regulation and decoupling provides the efficient power delivery needed to build a new processor subsystem with 40% more processor cores than the zEC12. The memory bandwidth and capacity have more than tripled, and the input/output bandwidth of the processor chip doubled to provide excellent scalability at the processor socket, drawer, and system level. The electronic packaging has been designed to meet all of these challenges, and this paper presents the design and integration of the electronic packaging of the z13 system.

Thermal Composites of Biobased Polyamide with Boron Nitride Micro Networks

Abstract: With the growing awareness of the damage sustained by environment, and the nearly-ubiquitous impulse to minimize and counteract this damage, the use of renewable (green) resources is becoming increasingly popular. Electronic industry continues to produce millions of electronic devices daily and the rapid growth of modern technology reduces these devices’ useable life spans. As a result, it has become increasingly imperative to find solutions for recycling these devices. Furthermore, since electronic devices are constantly becoming smaller and more powerful, accumulating heat concentration further reduces efficiency. Therefore, heat dissipation plays a very important role in modern electronic packaging applications. Bio-based high thermally conductive Polymeric composites seem to be potentially suitable replacements for current electronic packaging. These composites promise improved thermal management of electronics as well as protection from non-recyclable oil-based products in the environment. In this research, parametric study on partially bio-based polyamide (PA) in composite with micron size hexagonal boron nitride (hBN) platelets were performed. High viscosity PA90 and low viscosity PA30, both in composites with high thermally conductive hBN, were compared to determine the effect of matrix viscosity on mobility and arrangement of hBN particles, as well as effective thermal conductivity of the composite. Low viscosity PA30 consistently maintained higher values of thermal conductivity than the PA90. However PA90 shows higher mechanical properties. Furthermore, by narrowing down the filler content difference of the sample an interesting nonlinear trend between filler content and effective thermal conductivity of the composite is observed.

Steady-state low thermal resistance characterization apparatus: The bulk thermal tester

Abstract: The reliability of microelectronic devices is largely dependent on electronic packaging, which includes heat removal. The appropriate packaging design therefore necessitates precise knowledge of the relevant material properties, including thermal resistance and thermal conductivity. Thin materials and high conductivity layers make their thermal characterization challenging. A steady state measurement technique is presented and evaluated with the purpose to characterize samples with a thermal resistance below 100 mm(2) K/W. It is based on the heat flow meter bar approach made up by two copper blocks and relies exclusively on temperature measurements from thermocouples. The importance of thermocouple calibration is emphasized in order to obtain accurate temperature readings. An in depth error analysis, based on Gaussian error propagation, is carried out. An error sensitivity analysis highlights the importance of the precise knowledge of the thermal interface materials required for the measurements. Reference measurements on Mo samples reveal a measurement uncertainty in the range of 5% and most accurate measurements are obtained at high heat fluxes. Measurement techniques for homogeneous bulk samples, layered materials, and protruding cavity samples are discussed. Ultimately, a comprehensive overview of a steady state thermal characterization technique is provided, evaluating the accuracy of sample measurements with thermal resistances well below state of the art setups. Accurate characterization of materials used in heat removal applications, such as electronic packaging, will enable more efficient designs and ultimately contribute to energy savings.

Acceleration of lifetime modeling by isothermal bending fatigue tests

Abstract: The generation of meaningful lifetime-models is a serious and time-consuming challenge throughout the field of packaging. Wherever different materials are joined, the CTE mismatch will usually lead to thermo-mechanical fatigue due to the temperature cycles during the usage of the system [1–3]. As a result, the fatigue of interconnections is the limiting factor for reliability of electronic systems [4]. Usually lifetime investigations are executed as active or passive thermal cycles using the final systems with fixed amplitudes. The main objective is rather the validation that the system will exceed a minimum threshold than the developing of a full lifetime-model. Detailed investigations are often bypassed due to time and financial limitations not realizing the future benefits of a lifetime-model, i.e. by gaining understanding of failure mechanisms and the possibility to predict them by modelling [5–9]. Especially for interfaces based on new developed and mostly insufficiently examined materials like sintered (porous) or composite with their predicted time-depending or highly anisotropic behavior, more detailed experiments are necessary to understand the physics of failure. Such results are required for the technology developing and optimization of fatigue behavior. Therefor more experiments with samples of different technology-parameters as well as different amplitudes or load-regimes are necessary to examine the stability of failure mechanisms and the damage accumulation. New concepts to conduct such lifetime investigations faster are urgently needed [5]. The idea presented in this paper is to show a suitable method to substitute lengthy thermal cycling tests by results obtained by rapid isothermal fatigue tests at different temperatures and how to establish a correlation between both of them. For now, samples based on galvanically deposited copper are used as common reference-material. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed. In conclusion, this work shows a approach for a significant acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the thermal cycling test (TCT) samples and should show the same failure mechanism. Detailed investigations are still needed to confirm an applicability of the method also to other metal layers used in the electronic packaging industry.

Preparation method of electronic packaging silicon carbide reinforced aluminum-based composite material

Abstract: Disclosed is a preparation method of an electronic packaging silicon carbide reinforced aluminum-based composite material. The method comprises, firstly, performing pretreatment of coarsening, sensitization, activation, dispergation and drying on the surface of silicon carbide particles (SiCp); secondly, plating copper onto the surface of the SiCp at a PH value of 11-12.5 and a temperature of 35-47 DEG C with a plating solution composed of 5-12.5 g/l copper sulfate, 10-20 g/l EDTA (ethylene diamine tetraacetic acid), 5-15 g/l potassium sodium tartrate, formaldehyde with a volume fraction of 1.2-1.5% and methanol with a volume fraction of 0.7-0.9%; thirdly, preparing the aluminum-based composite material with a volume fraction of the SiCp of 50-55% through pressure-free infiltration. The preparation method of the electronic packaging silicon carbide reinforced aluminum-based composite material is simple in process and environmentally friendly; the prepared electronic packaging silicon carbide reinforced aluminum-based composite material is high in specific strength, specific stiffness and abrasive resistance and low in thermal expansion coefficients and greatly improves the thermal conductivity, thereby well solving the problem that electronic packaging materials are too high in temperature to result in effect failure of electronic elements.

Electronic packaging module and manufacturing method thereof

Abstract: The invention discloses an electronic packaging module and a manufacturing method thereof. The method comprises the following steps: providing a substrate, wherein the substrate is provided with an upper surface and comprises a grounding pad, and the grounding pad is exposed to the upper surface; arranging an electronic component on the upper surface and electrically connecting the electronic component with the substrate; covering the electronic component on the upper surface by use of a packaging body, wherein the packaging body is provided with a side surface; forming a groove in the packaging body so as to divide the packaging body into at least two packaging compartments, wherein the groove is exposed out of the grounding pad, the end part of the groove is positioned in the packaging body and is not in contact with the side surface; filling the groove with a conducting material so as to cover the surface of the groove to form a compartment shielding structure, wherein the compartment shielding structure is provided with a lateral wide face and a lateral long face and is connected with the grounding pad; removing part of the packaging body adjacent to the end part, which corresponds to the groove, of the side surface so as to respectively form a notch, wherein the notches are exposed out of the lateral wide face of the compartment shielding structure; forming an electromagnetic shielding layer to cover the surface of the packaging body and the compartment shielding structure and connecting the electromagnetic shielding layer with the lateral wide face by virtue of the notches.

Reliability study of lead-free solders under specific conditions

Abstract: Currently, accompanying the development of microelectronic joining and packaging, the integrated level of integrated circuit among the electronic devices has been substantially improved, which means the number of the soldered joints on a device is becoming more and more while the size of the micro-joint turns to be smaller and smaller. Given that soldered joints do play an important role in electronic packaging, serving as both mechanical bridges and electrical interconnections between the components and the bonding pads, to investigate the sensitivity of reliability of lead-free solders to various severe conditions deserves considerable concerns. This paper introduces the recent reliability research of lead-free solders under several specific conditions (e.g., isothermal aging, corrosive environment, drop impact, radiation) comprehensively, producing a fundamental summarization for the further reliability research.

A review of key development areas in low-cost packaging and integration of future E-band mm-wave transceivers

Abstract: With an ever increasing number of broadband applications in sub-Saharan Africa, mm-wave point-to-point networking has the potential to fill a niche in communications network architectures. Widespread adoption of this technology would benefit from conventional RF soft substrate integration and packaging, as opposed to system-on-chip or thick film processes. A review on the state-of-the-art in E-band soft substrate systems reveals significant reliance on MMICs. We propose that hybrid integration of active devices with off-chip passives, as well as better integration of active components in SIW, will lead to better performing E-band systems in soft substrates. Specific enabling techniques from the microwave domain are identified.

Synthesis with Glucose Reduction Method and Low Temperature Sintering of Ag-Cu Alloy Nanoparticle Pastes for Electronic Packaging

Abstract: The metallic nanoparticle paste is receiving great interests recently because it is a potential interconnect material which can perform joining at low temperature and serves at high temperature. The nano-Ag paste and nano-Cu paste have been the hot areas of research, whereas the high cost and low resistance of electrochemical migration of the former and the relatively low anti-oxidation property of the latter limit their applications. In this study, Ag-Cu alloy nanoparticles with the size of 20­50 nm were synthesized with glucose as the reducing agent and NaOH as accelerator. The Ag-Cu nanoparticle paste showed no oxidation after sintering up to 350°C in the air, indicating that the antioxidant capacity was superior to that of the mechanically mixed Ag nanoparticles and Cu nanoparticles. In addition, the electrochemical migration resistance of the sintered Ag-Cu alloy pastes was better than that of the Ag nanoparticle paste. This paste can be used to effectively bond silver-plated copper bulks with maximum shear strength of 35MPa. [doi:10.2320/matertrans.MI201406]

A metal oxide adhesion layer prepared with water based coating solution for wet Cu metallization of glass interposer

Abstract: Inorganic interposers made of glass are attractive for advanced high frequency applications and ultra- fine line patterning technology. Because glass combines a couple of benefits like large form factor, good coefficient of thermal expansion (CTE) matching to silicon, smooth surface and a low dielectric constant and loss tangent. Recently much progress has been made with respect to glass electrical and physical properties. This allows for handling of thin glass sheets down to 100 μm in a typical PCB panel format. Also advances have been made in the area of laser drilling allowing aspect ratio up to 1:10 for 25 μm diameter of through glass via (TGV). Another major challenge is the cost competitive and reliable metallization of smooth glass, a critical prerequisite for the use of glass substrates in the electronic packaging market. Plated copper does not adhere directly to glass. Sputtering technology typically also requires a 50 nm thick adhesion promoting metal layer (like Ti) before copper can be seeded....

Thermal compression bonding for fine pitch solder interconnects

Abstract: Thermal Compression Flip Chip bonding (TCFC) is a new interconnection technology in electronic packaging. With decreasing pitch of solder interconnects, traditional mass reflow solder bump faces the risk of shorting and non-wets for very fine pitch devices. The drive for ever-increasing numbers of interconnects, coupled with limited package size, necessitates finer pitch flip-chip solutions. In this paper, we introduce a TCFC-bonded copper pillar with solder cap interconnect solution, using non-conductive paste (NCP) on a laminate substrate with busless surface finish. This TCFC interconnect provides improved ELK performance relative to traditional mass reflow. The challenges to achieve a reliable TCFC solder joint structure will be discussed from different aspects such as assembly process, substrate surface finish and reliability testing.

Packaging layer, electronic packaging device and display device

Abstract: The embodiment of the invention provides a packaging layer, an electronic packaging device and a display device, and relates to the technical field of electronics. The thickness of the packaging layer can be reduced, and therefore the electronic packaging device can be light and thin. The packaging layer comprises a packaging isolation layer and an organic coating. The organic coating can be a polymerizable organic coating. The polymerizable organic coating comprises an unsaturated acrylics organic coating. The electronic packaging device is used for packaging electronic devices.

Challenges of wafer-level MEMS packaging

Abstract: Today's packaging standard for consumer MEMS sensors are plastic mold packages of the LGA or QFN type. Multiple chips are placed on a substrate or leadframe, electrically connected by wire bonds and protected by overmolding the sensitive devices. While being a flexible and very effective packaging technology it contributes significantly to the overall sensor dimensions in x-, y- and z-direction. The main driving forces for further market penetration of consumer MEMS sensors are however further thickness and footprint reduction, while retaining performance and reliability at lowest cost. The obvious approach to achieve these required reductions are new packaging technologies that partly or completely remove the substrate, the wire bonds and the encapsulation mold material. This is why we consider wafer level packaging being the future of Consumer MEMS. It will be presented that wafer level MEMS packaging of existing products already realizes a massive reduction of the sensor dimensions while mastering the challenges of this new technology.

Application of Aerosol Jet technology in through-via interconnection for MEMS wafer-level packaging

Abstract: In this paper, a novel method to achieve through-via interconnection using Aerosol Jet technology is proposed. Compared with the conventional MEMS through-via metallization e.g., coating with shadow mask or electroforming, the Aerosol process is (1) Adapt to extremely confined geometries of via, (2) Save material due to depositing on demand, (3) Allow to pattern the extraction electrode without mask. To demonstrate the method, printed Ag on doped silicon sintering from 200 to 500 °C is prepared and evaluated by testing which reveals a sufficient specific contact resistance. Besides, as the SEM cross sections show, metal layer is with good coverage for trapezium or even reverse trapezium via using the Aerosol Jet. However, the printed Ag is vulnerable to thermal shock and prone to crack after sintering. The corresponding cracks, resulting from residual tensile stress caused by the difference of thermal expansion coefficients, can be greatly eliminated by naturally cooling down.

Electronic packaging of SiC MOSFET-based devices for reliable high temperature operation

Abstract: Silicon carbide (SiC) devices allow electronics to operate at high junction temperatures (>200°C) and high voltages (>10 kV). In addition, they provide faster switching and lower power losses than their silicon-based counterparts. Recently, MOSFET (metal-oxide semiconductor field effect transistor) devices were demonstrated to work up to 500°C. Robust packaging solutions are needed to take advantage of the extreme temperature capability in the areas of propulsion, power generation, and oil/natural gas exploration. This paper reviews the current packaging challenges for 400–500°C operation temperature, and presents a hermetic package solution for reliable operation.

Indirect Contact Probing Method for Characterizing Vertical Interconnections in Electronic Packaging

Abstract: This letter proposes a new indirect contact probing method to characterize vertical interconnections without contact damage. At the first step of the proposed technique, multiple one-port calibration measurements should be performed to characterize the contactor layer between the probe pads and the device-under-tests (DUTs). The characteristics of the actual vias as the DUTs are then extracted from indirect-contact measurements by de-embedding the contactor layer. In simulations and experiments at frequencies range from 2.5 to 18 GHz, we have verified via defects can be successfully identified from the indirect-contact measurements.

Characterization of Nanomaterials for Interconnect and Thermal Management in Electronic Packaging

Abstract: Electronic packaging, protecting the fragile chip from atmosphere and providing the paths for signal transmission as well as heat dissipation, is one of the most important parts in electronic devices. The cost, dimensions, performance, and reliability of an electronic device therefore strongly depend on its packaging structures and materials. In recent years, the miniaturization and diversification of electrical devices, having increased packaging and power density, pose a serious challenge to the reliability of traditional packaging materials. To address this challenge, several nanomaterials were thus fabricated and used for either interconnection or heat dissipation in the electronic packaging. For interconnection, vertically aligned carbon nanotubes (VACNT) grown with thermal chemical vapor deposition (TCVD) method were used as filling materials of through silicon vias (TSV). Meanwhile, vertically aligned carbon nanofibers (VACNF) fabricated with plasma enhanced chemical vapor deposition (PECVD) method were used as not only the bump material for chips, but also for the reinforcement material for solder joints. By using these carbon nanomaterials, some failure modes, such as burnout, electromigration, and coarseness, can be avoided. Besides carbon, alloy and semiconductor nanomaterials were also fabricated in this thesis for interconnection. Sn3.0Ag0.5Cu (SAC305) alloy and Bi2Te3 semiconductor nanopowders were mixed with traditional Sn58Bi and SAC305 lead free solders respectively in order to improve the shear strength and thermal fatigue resistance of solder joints. The dislocation movement and crack propagation can be effectively delayed by uniformly distributed nanoparticles in the solder matrix. However, it always shows a performance degradation when the content of nanoparticles passes a threshold. This phenomenon could be caused by increased voids and the agglomeration of nanoparticles in the solder matrix with increased content of nanoparticles. For heat dissipation, a polyimide (PI) network enhanced indium thermal interface material (TIM) was developed as a passive heat dissipation solution, and meanwhile a nanostructured bulk thermoelectric (TE) material constructed of Ag and Bi2Te3 nanopowders is presented as an active heat dissipation solution. The mechanical properties of pure indium TIM can be improved by the PI network without any degradation of heat dissipation ability. This is attributed to the Ag-coated PI fibers which formed solid bonding with the indium matrix and constrained the crack propagation. For the TE material, the thermal conductivity of nanostructured Bi2Te3 samples was much lower than that of raw materials due to the increased phonon scattering at the grain boundaries, which consequently led to a higher figure of merit (ZT value).