Showing papers on "Electronic packaging published in 2017"

Novel organic–inorganic composites with high thermal conductivity for electronic packaging applications: A key issue review

Abstract: Significant progress has been made recently in developing the organic–inorganic composites with high thermal conductivity, low dielectric constant, and dielectric loss, for applications in the electronic packaging and substrates. Many studies have shown that some polymers filled with high thermal conductivity and low dielectric loss ceramics are suitable for electronic packaging for device encapsulation. Until now, extensive attentions have been paid to the preparation of polymeric composites with high thermal conductivity and low dielectric loss for the application in electronic packaging. In contrast, the thermal conductivities of these dielectric materials are still not high enough and that might restrict their serviceable range. Herein, we briefly reviewed recent progress in this field and introduced a kind of novel composites with surface insulation modified metal aluminum cores to form multilayer coating structures as fillers in polyimide matrix for electronic applications. This structure can significantly improve the thermal conductivity and dielectric properties of composites and give some insights into the effects of modified fillers of composite materials. Such multilayer core–shell structures should have great potentials for the improvement of nanoparticle-based fillers and applications of electronic packaging. POLYM. COMPOS., 2015. © 2015 Society of Plastics Engineers

Manipulating Orientation of Silicon Carbide Nanowire in Polymer Composites to Achieve High Thermal Conductivity

Abstract: Highly thermally conductive polymer composites have received considerable attention, along with development of electronic devices toward being more integrated, miniaturized, and functionalized. However, traditional polymer composites cannot meet the requirement of achieving higher thermal conductivity at relatively low filler loading. Herein, manipulating orientation of silicon carbide nanowire (SiCNW) in epoxy composites by coating method is reported to achieve high in-plane thermal conductivity (10.10 W m−1 K−1) at extremely low filler loading (5 wt%), while it is only 1.78 and 0.30 W m−1 K−1 for epoxy/random SiCNW composite and epoxy/silicon carbide nanoparticle composite. Several models are employed to demonstrate that a good orientation and high aspect ratio of SiCNWs contribute to form heat transfer networks in the composites. This provides a promising future for thermal-management materials, which are widely applied to electronic packaging, aerospace field, and medical engineering.

A critical review of constitutive models for solders in electronic packaging

Abstract: Owing to their superior electrical, thermal, and mechanical properties, solder joints are the most widely used interconnection materials in electronic product packaging. Because the failure of the ...

Synthesis of silver nanoparticles using large-area arc discharge and its application in electronic packaging

Abstract: Silver nanoparticles were efficiently synthesized by large-area arc discharge in liquid and were found to be effective as bonding materials in power microelectronic packaging. The results showed that the production rate of silver nanoparticles depended on the heat input during processing and reached the maximum value of 350 mg/min at current 104 A, which was much higher than any previously reported productivity by the arc discharge method. The silver nanoparticles were characterized in terms of their microstructure, morphology, particle size, and distribution. Two Gaussian peaks were found in the nanoparticle size distribution curve, which were 33 and 220 nm, respectively. This mixed-size nanoparticle paste was naturally economical and effective for the packaging application due to the combination of the high surface energy of small nanoparticles and the efficient joint filling of the large nanoparticles. The cross-section microstructure and fracture surface of bonded joints indicated that atomic bonds formed between the sintered layer and the substrates. Additionally, the mechanism of arc discharge for synthesizing the silver nanoparticles was discussed.

Reliability assessment using modified energy based model for WLCSP solder joints

Abstract: The reliability life assessment of electronic packages is a key issue to ensure the mass production quality of packaging components. To meet the time-to-market and long term reliability requirements, using finite element to predict a precise life cycle of solder joints becomes the main trend of electronic packaging product development. Thermal cycling test is a standard test and has been widely used for testing long term reliability of packaging components, however, many cases shown the ramp rate will affect the reliability life of solder joint, therefore, the strain rate and creep effect should take into account for life prediction in finite element simulation. Our previous results found the life prediction is not accurate enough when using Darveaux energy based model for solder joint's life prediction. In this research, based on the optimal mesh size, we modify the energy based model to a simplified form based on our wafer level chip-scale packaging (WLCSP) study results, and this modified empirical solution can provide a better reliability life prediction than conventional energy based model. If the dwell time and ramp rate are fixed, the effect of time dependent creep behavior become inconspicuous. Based on our optimal mesh size, Coffin-Manson strain based model can also predict a precise lifetime and even with less computing time.

Design and Reliability Assessment of Novel 3D-IC Packaging

Abstract: Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

3D Printing as a New Packaging Approach for MEMS and Electronic Devices

Abstract: In this paper we present a new approach for building specific packaging that is scalable, versatile and could be potentially cost competitive. Using polymer additive manufacturing, more commonly known as 3D printing, we set out to build customized structures and packages perfectly adapted to component dimensions and specifications. Two different 3D printing technologies, respectively called stereolithography and Fused Deposition Molding, were studied. The work described in this paper opens plenty of new approaches: device design with a customizable backend packaging process, packaging adapted to each different component, even on the same device, fast device prototyping with accurate characteristics, among others. Our main observation is that the stereolithography technology is compatible with microelectronics substrates. Another technology, fused deposition molding, was also tested, but was not well adapted to packaging components, the major incompatibilities being the inability to print on silicon and some coarser dimensions than those required for microelectronic applications. We argue that specific patterns for the printed structure and compatibility between substrate and printed material (which can be improved with surface modifications) are key requirements to obtain the expected results.

A design of a new miniature device for solder joints’ mechanical properties evaluation:

Abstract: This paper makes a focus on the design of a micro-testing machine used for evaluating the mechanical properties of solder alloys. The different parts of the testing device have been developed and assembled in a manner that will facilitate the study of miniature solder joints as used in electronic packaging. A specific procedure for fabricating miniature lap-shear joint specimens is proposed in this work. The tests carried out with the newly developed machine serve to determine the material behavior of solder joints under different controlled loading and temperature conditions. Two new solder alloys, namely SACBiNi and Innolot, are characterized in the study, showing the influence of strain rate and temperature parameters on their respective mechanical responses. In addition, the as-cast and fracture surfaces of the solder joints are observed with a scanning electron microscope to reveal the degradation mechanisms. The SACBiNi solder alloy, which contains less Ni and Sb elements, is found to have smaller s...

Thermal Analysis of Solder Joint Based on Eddy Current Pulsed Thermography

Abstract: Solder joint provides electronic and mechanical connections between components and substrate. Overheating and excessive temperature gradient can cause solder joint failures and then make the whole system break down. Thus, thermal analysis has been the hotspot in reliability evaluation of electronic packaging. This paper proposes eddy current pulsed thermography (ECPT) to investigate thermal transfer through solder joint in a surface mounted device (SMD). A 3-D electromagnetic-thermal model was built, and the ECPT system was established to analyze transient temperature distribution on the pin surface. This model introduced pseudo soldering and evaluated its impacts on thermal conduction. Thermal resistance of solder joint was calculated to characterize different pseudo soldering defects. With pseudo soldering acreage increased, thermal resistance had an approximate quadratic rise. Both simulation and experimental results indicate that the surface temperature gradually decreases with the increase of pseudo soldering acreage. This ECPT method could be applied to the thermal analysis of solder joint in SMD, and it also could provide guidance for thermal design or reliability evaluation of electronic packages.

Visible laser welding of electronic packaging, automotive electrics, battery and other components

Abstract: A visible light laser system and operation for welding materials together. A blue laser system and operation for welding conductive elements, and in particular thin conductive elements, together for use in energy storage devices, such as battery packs.

Thermal performance evaluation of different passive devices for electronics cooling

Abstract: The advent of modern electronic technology lead to miniaturization and high power density of electronic devices, then the existing electronic cooling techniques cannot be used, directly affecting the performance, cost, and reliability of electronic devices. Thus, the thermal management of electronic packaging has become a key technique in many products. Passive heat transfer devices can be a good alternative to the stabilization of electronic devices temperature. In this re-search, an experimental evaluation of the thermal performance of four different passive devices was accomplished. The considered devices were a rod, a thermosyphon, a heat pipe with a metal screen as the capillary structure, and a heat pipe with microgrooves. The heat pipe is a highly efficient device that carries large amounts of power with a small temperature difference. The heat pipe consists of the involucre, the working fluid, and the capillary structure. The thermosyphon is a kind of heat pipe assisted by gravity. In other words, it has no wick structure to return the working fluid. The devices were made of copper with a total length of 200 mm and an outer diameter of 9.45 mm. The thermosyphon and the heat pipes used deionized water as working fluid with a filling ratio of 60% of the evaporator volume. The devices were tested in vertical and horizontal positions under thermal loads between 5 W and 45 W. All the devices have operated satisfactorily when tested in accordance with the behavior of the thermal resistance. The heat pipes were the best among the tested devices and the best position was vertical.

Concepts for embedded cooling of vertical current wide band-gap semiconductor devices

Abstract: Wide band-gap (WBG) power semiconductor devices are being researched in order to meet future high power density electronic packaging targets for a range of power conversion applications. All power devices may be classified based on the current flow direction, namely lateral versus vertical, and for both types, the device junction temperature is determined, in part, by the package thermal resistance. For electrified vehicle applications, where vertical current device architectures are preferred, the vertical configuration leads to current rates that are higher than those found in a lateral device, and this in turn leads to large heat fluxes (∼1 kW/cm2) for large bare dies (∼1 cm2). Considering the challenges associated with the vertical current WBG device structure, three embedded cooling concepts are described. One strategy is selected for initial investigation, where a multi-layer straight microchannel chip-scale cooler is fabricated and thermal-fluid performance characteristics of the device are experimentally plus numerically evaluated. Performance limitations of the design are highlighted, and ongoing work focused on fabrication of a design that exploits jet impingement plus fluid flow through an optimized microchannel topology is described. Discussion regarding device electrical performance and the separation of the vertical current field from the coolant flow is provided.

Assembly and Reliability Challenges for Next Generation High Thermal TIM Materials

Abstract: High power consumption & high input/out (IO) density are requested by modem electronic components such as high-density electronics, communication satellites, advanced aircraft, networking server and telecommunication devices. Challenges in the heat dissipation of an electronic package arise from the continued increase in power dissipation and power density of higher-power devices. A thermal interface material (TIM) with excellent heat conduction coefficient is applied between the heat source surface and the heat-spreading module. This is to efficiently dissipate heat from the heat source. Thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Therefore, beside the thermal properties, a good mechanical strength of TIM is required. In order to meet demands for higher thermal performance and reliability strength needs in modem electronic devices, various new TIM materials were proposed by industry leading material suppliers. Some of the leading new TIM materials used for this purpose are graphite based and metal based materials where thermal conductivity could be higher than epoxy based TIM materials. In this paper, we will compare new graphite based and metal based TIM materials with existing epoxy based TIM materials and will discuss the various assembly challenges and reliability performance of these new TIM materials. Compare to commercial TIM, the graphite based TIM provide a heat conduction path in a direction perpendicular, metal based TIM is disposed in the Nano-particle metal by sintering to consist of heat conduction path. The junction temperature (Tj) of metal based TIM material shows 5 degrees C decreased than epoxy based material. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) post reliability testing. Moreover, thermal simulations will be conducted and presented in this paper.

Thermal interface material characterization for cryogenic electronic packaging solutions

Abstract: As applications of superconducting logic technologies continue to grow, the need for efficient and reliable cryogenic packaging becomes crucial to development and testing. A trade study of materials was done to develop a practical understanding of the properties of interface materials around 4 K. While literature exists for varying interface tests, discrepancies are found in the reported performance of different materials and in the ranges of applied force in which they are optimal. In considering applications extending from top cooling a silicon chip to clamping a heat sink, a range of forces from approximately 44 N to approximately 445 N was chosen for testing different interface materials. For each range of forces a single material was identified to optimize the thermal conductance of the joint. Of the tested interfaces, indium foil clamped at approximately 445 N showed the highest thermal conductance. Results are presented from these characterizations and useful methodologies for efficient testing are defined.

The Complete Packaging Reliability Studies through One Digital Image Correlation System

Abstract: Three-dimensional (3-D) digital image correlation (DIC) has been gradually adopted by industry these years. This method utilizes a pair of cameras to accumulate and correlate images through tracking the movement of features on the specimen surface in real time. It is capable of generating both in-plane and out-of-plane deformation during one test. To some extent, it is perfect to be utilized in the reliability analysis for electronic packages due to its high measurement accuracy and adjustable field of view. Therefore, it attracts much attention from the electronic packaging area. In this work, several reliability studies of the electronic packages with 3-D DIC system were introduced. The advantages of DIC were discussed and some features were compared to the conventional measurement methods. At the same time, the methodology, to make full use of this technique to achieve most information with DIC system, was described. With one DIC system, the 2-D strain measurement of solders, micro-bumps and the underfill can be done to learn the internal residual stress and strain distribution under loading. Meanwhile, both CTE and warpage results were generated by the 3-D DIC experiment by one measurement for assessing the reliability of the packages and validating the effectiveness of the finite element models.

Integration of silicon photonics IC for high data rate

Abstract: Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.

Development and First Assessment of a DIC System for a Micro-Tensile Tester Used for Solder Characterization

Abstract: Characterization of solder alloys is of primary importance for manufacturers due to the wide use of these alloys as interconnects for electronic packaging. Numerous investigations have so far been dedicated to determination of their mechanical properties like their creep response under thermo-mechanical loading, in particular. There is a broad variety of experimental devices and techniques that the researchers employed to study the different types of solders. We have recently designed a micro-tensile tester to characterize miniature solder specimens under various conditions of temperature and extension rate. In the present work, this experimental apparatus is complemented with imaging equipment, giving the ability to perform Digital Image Correlation (DIC) for full-field measurements on solder materials. The suitability and accuracy of both the optical system and the DIC technique for tin-based alloys characterization are first evaluated, based on specific assessment criteria. It is found that the system resolution is sufficient to obtain reliable results. A full-field strain measurement is then done by testing a standard specimen. Materials parameters, such as the elastic constants, are extracted from DIC data and compared with the measures obtained from the conventional sensors equipping the micro-tester, showing the ability of the newly designed optical system to be used in the small strain range. The study of necking has also been proven to be accurate with this system, allowing the precise evaluation of the highly localized strain in the specimen.

Novel Polymer Substrate-Based 1.2 kV/40: A Double-Sided Intelligent Power Module

Abstract: Advanced power module packaging technology is currently being heavily investigated to take full advantage of Wide Band Gap (WBG) power semiconductor devices. As one of most widely applied power module technologies, intelligent power modules, typically for automotive industries, work well to achieve higher operating frequencies with lower losses by integrating gate driver circuits with power semiconductor devices. In this paper, a novel flexible polymer substrate-based intelligent power module is developed and characterized. By applying 80 µm-thick epoxy-resin based flexible dielectric as a substrate, the overall weight and volume of the power module is reduced, as well as the cost, compared with traditional direct bonded copper ceramic-based modules. The performance of the epoxy-resin based dielectric is investigated, and shows that the leakage current of the dielectric at >1.5 kV is less than 20 µA at 250 oC. Double-sided solderable 1.2 kV SiC MOSFETs and Schottky diodes are fabricated and applied in the module without bonding wires, significantly reducing the overall parasitic inductance to

Method for preparing electronic packaging microscale solder joints

Abstract: The invention relates to a method for preparing electronic packaging microscale solder joints. The method includes the steps that first metal bonding pads, first weldable layers and micro convex points are sequentially prepared on a first substrate; second metal bonding pads and second weldable layers are sequentially prepared on a second substrate; the micro convex points and the second metal bonding pads align with each other in a one-to-one mode and are placed in a contact mode, so that an assembly is formed; a required reflow profile is selected for brazing backflow of the assembly; and the assembly sequentially passes through a preheating zone, a backflow zone and a cooling zone, a temperature gradient is formed between the first metal bonding pads and the second metal bonding pads and located in the cooling zone until the micro convex points are completely changed to be in the solid state from the liquid state, and accordingly the microscale solder joints are formed. By the adoption of the method, Sn crystal orientation in a brazing filler metal matrix of the microscale solder joints can be adjusted and controlled, the formed single preferred orientation microscale solder joints can achieve good compatibility with semiconductors and the packaging technology, electro migration and thermal migration resistance stability is good, interconnection between the first substrate and the second substrate can be achieved, and the service life of the microscale solder joints or devices with the material organization or structural features is prolonged.

Multi-physics models and condition-based monitoring for 3D-Printing of electronic packages

Abstract: 3D-Printing technology, or additive manufacturing, is seeing increased interest in the electronic packaging community as it has the potential to enable cost-effective, potentially high-throughput and high degree of design customisation. At the same time there are a number of challenges related to quality, performance and reliability of the fabricated products. Technological advances and other capabilities to address successfully these challenges are required and need to be developed. This include the development of process models that can be used to predict characteristics of products manufactured with 3D printing techniques. This paper gives an overview of the current state of 3D printing in the context of technology use for electronics packaging. It details in particular the developments made in the modelling for 3D ink-jet printing of packaged electronic components which is taking place in the EU funded project NextFactory (http://www.nextfactory-project.eu). This project is developing an all-in-one manufacturing platform that integrates 3D-printing (multi-material ink-jet), material cure and sintering and micro-assembly technologies for electronic packaging applications. Particular areas of novelty in the presented work relate to: (1) development of Smooth Particle Hydrodynamics solver for ink-jet droplet deposition and coalescence, (2) development of finite element models for predicting deformation and residual stress due to cure shrinkage as each layer is deposited, and (3) development of machine-learning and surrogate modelling based framework for condition-based monitoring of the fabrication process.

Thermo-mechanical reliability analysis of flip-chip bonded silicon carbide Schottky diodes

Abstract: This paper presents the thermo-mechanical reliability analysis of a novel chip-scale wire bondless packaging technique for a SiC Schottky diode that leads to lower parasitics, higher reliability, lower costs, and lower losses The proposed approach uses a flip-chip solder ball array to make connections to the anode A copper connector was used to make contact with the bottom cathode, thus reconfiguring the bare die into a chip-scale, flip-chip capable device Thermo-mechanical analysis in a finite element software showed that the proposed approach could better manage Coefficient of Thermal Expansion (CTE) mismatch stresses arising at the critical module interfaces as compared with a conventional wire bonded module A detailed analysis of the flip-chip structure is presented and contrasted with a state-of-the-art wire bonded module Different design parameters were explored for the drain connector to be able to make an optimized decision However, keeping production costs low was prioritized without compromising significant performance The fabrication process for manufacturing a flip-chip schottky diode module was also demonstrated along with preliminary test results to demonstrate functionality

Process emulation for predicting die shift and wafer warpage in wafer reconstitution

Abstract: Wafer reconstitution is a vital process for serving as a buffer to decouple the processing developments between IC fabrication and electronics packaging. By this approach, the IC packaging is then independent from the chip processing. However, such a process brings numerous mechanical loadings during molding and curing phases. Without carefully planning, failures such as die-shifting and excessive wafer warpages are frequently reported and it induces problems for subsequent processing. In this work, it is desired to examine the key factor of die-shift and wafer warpage by performing both fluidic mold flow and solid thermo-mechanical analyses, as well as essential material characterizations. Preliminarily, the die-shift problem is deduced as interaction of fluid load, thermal expansion, shrinkage of molding compound and viscoelastic effect. To have a deeper insight, simplified fluid model and finite element analyses have been constructed to mimic the entire Recon process. For mold flow analysis, a simplified 1-D viscous flow analytical model is adapted. It aims to find the relationship between the molding parameters and the achieved velocity and pressure fields for calculating the possible drag and shear forces acting on dies for causing shift. On the other hand, after molding, the stress and deformation of the entire curing process is then performed by finite element method. The possible die shift and final warpage are then examined step by step to evaluate the contribution from each step and even each processing parameter. Both simplified 2-D axisymmetric and 3D models are performed and analyzed. The preliminary analysis results indicate that the thermal stress during curing is the current dominating factor. Related parameters such as the properties of compounds and carriers and the process parameters such as the curing temperature and duration could be the major controlling factors.

A Novel Organic Substrate with Enhanced Thermal Conductivity

Abstract: The continuing miniaturization and increasing power density of modern electronics make thermal-management a critical challenge for advanced materials used in electronic packaging field. As an important element of electronic packages, the thermal-conduction property of substrates plays an important role in heat removal. Polymer composites are commonly used in substrates because of their ease of large production, light weight, and excellent flexibility compared with ceramics. However, the traditional approaches to fabricating thermally conductive polymer composites usually suffer from a low thermal conductivity enhancement and/or the deterioration of mechanical property. In this study, using hexagonal boron nitride as thermally conductive filler and glass fibers as mechanically reinforced fillers liquid crystal epoxy composites, A kind of novel highly thermally conductive polymer composite that can be used as an organic substrate was prepared. The composite with a hexagonal boron nitride weight loading of 50 wt% exhibit the maximum in-plane and through-plane thermal conductivities of 5.85 and 1.60 W/m K, respectively. In addition, the polymer composites also possess good thermal stability, low dielectric permittivity, and excellent mechanical properties. This work provides a high thermally conductive organic substrate for advanced electronic packaging.

3.15 Electroless Plating as Surface Finishing in Electronic Packaging

Abstract: Electroless plating is one type of surface finish deposition method in electronic packaging. With advancements in electronic products, the industry is shifting toward this process based on its advantages. However, the electroless plating process itself is unstable. Its stability fully depends on the substrate material, the pretreatment process, the type of solution used, and the pH and temperature during plating. In this article, focus is given to the three different types of electroless plating formulations used in electronic packaging that have been studied by previous researchers: electroless nickel, electroless palladium, and electroless gold.

Test structures for the characterisation of sensor packaging technology

Abstract: This paper presents three test structures targeted at characterising sensor packaging materials for liquid environments. The test structures enable the evaluation of: 1) the successful removal of packaging material on sensing areas, 2) the permeability of the packaging material to its environment, 3) electrical continuity through the packaging process, and 4) the ingress of the liquid environment between the packaging material and the chip surface. The paper presents an example of the evaluation of a UV curable resin as packaging process for a biomedical sensor.