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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


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Journal Article
01 Jan 2001-Scopus
TL;DR: In this article, the failure modes of power electronics devices, especially IGBTs, are reviewed and a FEM analysis of a multilayered IGBT packaging module under cyclic thermal loading is presented.
Abstract: The development of power electronics technology is driven by the insatiate demand to control electrical power. The new power electronics devices reduce the volume of the converters by three to four orders of magnitude compared to their mercury arc predecessor. And the turn-on and turn-o0 time has decreased from milliseconds to the microseconds and even nanoseconds, depending on power level. The power range commanded by converters now extends from micro-VA to several hundreds of mega-MVA. Among the new power devices, insulated gate bipolar transistor (IGBT) devices are being more accepted and increasingly used in traction application such as locomotive, elevator, tram and subway. Thus the long-term reliability of IGBT is highly demanded. In this paper the failure modes of power electronics devices especially IGBTs are reviewed. A FEM analysis of a multilayered IGBT packaging module under cyclic thermal loading is presented.? 2001 Elsevier Science B.V. All rights reserved.

134 citations

Patent
21 Feb 2001
TL;DR: In this article, a new architecture for packaging surface micromachined electro-microfluidic devices is presented, which relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro scale (microliters).
Abstract: A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

130 citations

Journal ArticleDOI
TL;DR: In this paper, a new approach to vacuum packaging of micro-machined resonant, tunneling, and display devices is covered, where a multi-layer, thin-film getter, called a NanoGetter, which is particle free and does not increase the chip size of the micro system has been developed and integrated into conventional wafer-to-wafer bonding processes.
Abstract: A new approach to vacuum packaging of micro-machined resonant, tunneling, and display devices is covered in this paper. A multi-layer, thin-film getter, called a NanoGetter, which is particle free and does not increase the chip size of the microsystem has been developed and integrated into conventional wafer-to-wafer bonding processes. Hermetic electrical feedthroughs are also provided as part of this total-solution technology. Experimental data taken with silicon resonators is presented in which Q values in excess of 21,000 have been obtained. Applications for this technology include gyroscopes, accelerometers, displays, flow sensors, density meters, infrared (IR) sensors, microvacuum tubes, radio frequency microelectromechanical systems (RF-MEMS) and pressure sensors.

128 citations

Journal ArticleDOI
TL;DR: In this article, perfect magnetic conductor (PMC)-based packaging technique was used to improve the isolation performance among various microwave circuit components such as high-gain amplifier chains, and two Ka-band amplifier chains were tested with this new packaging technique.
Abstract: In this paper, perfect magnetic conductor (PMC)-based packaging technique was used to improve the isolation performance among various microwave circuit components such as high-gain amplifier chains. In this approach, a periodic structure (such as metal pin rows) together with the ground plane of the substrate created a stopband for unwanted parallel plate or cavity modes as well as substrate modes, and thereby suppressed the problems of circuit resonances and related package phenomena. This paper describes two Ka-band amplifier chains that were tested with this new packaging technique. Firstly, a single amplifier chain was tested for maximum stable gain operation, and it was found that the stable gain of was achieved, whereas traditional metal wall package with RF absorber offered stable gain of 40 dB, thus showing significant isolation improvement. Secondly, two high-gain amplifier chains were placed side by side and their mutual isolation was tested. With the proposed gap waveguide packaging, a minimum isolation of 78 dB was achieved, whereas a complete metal shield provided a minimum isolation of only 64 dB over the band of interest.

126 citations

Proceedings ArticleDOI
24 Apr 2006
TL;DR: This paper defines the key technologies for realizing true 3D interconnect schemes as respectively 3D-SIP,3D-WLP and 3d-SIC, which can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP approach and a foundry level ('below' passivation) approach.
Abstract: Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

126 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896