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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


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Journal ArticleDOI
TL;DR: A unified constitutive modeling approach based on the disturbed state concept (DSC) provides improved characterization of thermomechanical response of joining (solders), ceramics and printed wire board (PWB) materials in electronic packaging as mentioned in this paper.
Abstract: A unified constitutive modeling approach based on the disturbed state concept (DSC) provides improved characterization of thermomechanical response of joining (solders), ceramics and printed wire board (PWB) materials in electronic packaging. Various versions in the DSC approach are calibrated and validated with respect to laboratory test data, and are implemented in a nonlinear finite element (FE) procedure. The hierarchical nature of this procedure permits the user to choose a constitutive model, simple (elastic) to sophisticated (elastovisco-plastic with disturbance), depending upon the material and need. The FE is used to analyze thermomechanical behavior of two typical problems: (1) leadless ceramic chip carrier (LCCC) package; (2) solder ball connect (SBC) package. The FE results under cyclic thermal loading are compared with experimental data for the two packages, and with a previous FE analysis for the SBC package. In conjunction with the idea of critical disturbance at which thermal fatigue failure can occur, the analyzes allow identification of cycles to failure, N/sub f/, and evaluation of reliability of the package. In the case of the SBC package, the analysis permits an evaluation of ball spacing on the thermomechanical behavior. The DSC approach can provide an integrated and improved procedure compared to available models for elastic, plastic, creep strains, and microcracking leading to degradation of strength and fatigue failure for a wide range of problems in electronic packaging under thermomechanical loading.

23 citations

Journal ArticleDOI
TL;DR: In this paper, the authors used FEMLAB multi-physics software to predict the thermal stress and strain in a complex device under thermal loads and the corresponding lifetime of the device.
Abstract: Due to the increasing complexity, miniaturization and higher density of components in modern devices, reliability and lifetime are important issues in electronic packaging. In modern electronic devices, the packaged structure consists of a variety of metallic, ceramic, plastic or composites components. The large differences in coefficient of thermal expansion (CTE) between ceramic substrates (such as Al2O3 and AlN) heat dissipation materials (such as Cu and Al,) and semiconductors (such as Si and GaAs) induce thermal stress and therefore possible thermal failure in solder joints or ceramic substrates. As a result, to ensure the reliability of electronic devices at increased packing and power densities, thermal management must be considered as a critical aspect in the design of multi-chip modules. There is, therefore, a strong need for the development of new designs utilising novel heat dissipation materials with low coefficients of thermal expansion and high thermal conductivities. During the last decade, the developments in material selection and thermo-mechanical modelling software have lead to design optimisation of complex devices and the prediction of their lifetime.[1,2] It is very important to study material and design parameters that would improve reliability. The challenge is determining the thermal properties of new materials such as composites, which can be very powerful materials in controlling thermal stress and, as a result, increasing the reliability of electronic packages. In this paper, thermo-mechanical modelling predicts i) stress/strain responses in the electronic device under thermal loads, and ii) the corresponding reliability (lifetime). The thermal stress and strain analyses in this study have been performed with FEMLAB multi-physics software. Furthermore, it models the couple between different materials in complex device designs.

23 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal, mechanical, and dielectric properties of new high-performance polyphenylene sulfide/aluminum nitride (AlN) composites prepared by hot pressing were investigated for use in electronic packaging.
Abstract: The thermal, mechanical, and dielectric properties of new high-performance polyphenylene sulfide/aluminum nitride (AlN) composites prepared by hot pressing were investigated for use in electronic packaging. The coefficient of thermal expansion was decreased by 41%. The glass-transition temperature and Vickers microhardness were increased by 13°C and 46%, respectively, for the 15.1 vol.% AlN composite. A modified rule of mixtures with β of 0.065 fits the data. The dielectric constant and loss factor of the composites are within the range of requirements for commercial use.

23 citations

Proceedings ArticleDOI
12 Sep 1994
TL;DR: In this article, the evaluation results on the lead-free eutectic Sn-Ag solder for use in automotive electronics packaging applications are presented, and the major areas of study are the metallurgical interactions between the solder, the conductor and the component termination, and their impact on reliability.
Abstract: This paper presents the evaluation results on the lead-free eutectic Sn-Ag solder for use in automotive electronics packaging applications. The major areas of study are the metallurgical interactions between the solder, the conductor, and the component termination, and their impact on reliability. Studies have been conducted with the eutectic Sn/Pb solder as a control group for comparison. >

23 citations

Journal ArticleDOI
TL;DR: In this article, the fabrication process for an interconnect technology in silicon systems is described, which involves the electroplating of chemically etched through-holes in silicon substrates, which act as vias between the front and back sides of the substrate.
Abstract: This paper describes the fabrication process for an interconnect technology in silicon systems. The process involves the electroplating of chemically etched through-holes in silicon substrates. These plated holes act as vias between the front and back sides of the substrate. This method can be used in high-density multilayer three-dimensional systems to minimize the delay times between chips. It can also be used in the packaging of silicon sensors to address the problem of system partitioning. We report via resistance in the order of mΩ, isolation resistance between 1 to 3 GΩ, and capacitance less than 10 pE

23 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896