Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Through silicon via copper electrodeposition for 3D integration

Abstract: Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.

Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection

Abstract: This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of lowtemperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ~80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications.

Localized induction heating solder bonding for wafer level MEMS packaging

Abstract: This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

Self-assembly for microscale and nanoscale packaging: steps toward self-packaging

Abstract: The packaging of microelectromechanical systems (MEMS) and nanoscale devices constitutes an important area of research and development that is vital to the commercialization of such devices. Packaging needs of these devices include interfaces to nonelectronic domains; integration of structures, devices, and subsystems made with incompatible fabrication processes into a single platform; and the ability to handle a very large numbers of parts. Although serial, robotic assembly methods such as pick-and-place have allowed significant manufacturing feats, self-assembly is an attractive option to tackle packaging issues as the size of individual parts decreases below 300 /spl mu/m. In this paper, we review advances made in the usage of self-assembly for packaging and potential directions that growth in this area can assume. In the micrometer scale, we review the use of capillary forces, gravity, shape recognition, and electric fields to guide two- and three-dimensional self-assembly processes. In the nanoscale, we survey the usage of self-assembled molecular monolayers to solve current packaging issues, DNA hybridization for guiding self-assembly processes of nanoscale devices, and methods used to package nanowires or nanotubes into electronic circuits. We conclude with an example of a nanoscale biosensor which directly incorporates the concept of its package into its fabrication process. Even though the idea of a fully self-packaging system has not been demonstrated to date, the body of work reviewed and discussed here presents a solid foundation for the pursuit of this goal.