Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Graphite composites for electronic packaging

Abstract: There is provided a component for use in electronic packaging. The component is a composite having a graphite matrix which is infiltrated with a metal or a metal alloy and the external surfaces of the composite then coated with a metallic layer to provide environmental and mechanical protection. The packaging components are lightweight, have a coefficient of thermal expansion close to that of a silicon based integrated circuit device and further, have a high coefficient of thermal conductivity.

Bed of nails - 100 microns pitch wafer level interconnections process

Abstract: The rapid advances in IC design and fabrication continue to challenge the electronic packaging technology, in terms of fine pitch, high performance, low cost and better reliability In the near future, the demands for higher I/O count per integrated circuit (IC) chip increases as the shift towards the nano ICs with feature size less than 90nm To meet the above requirements, the chip-to-substrate interconnection technologies with less than 100/spl mu/m pitch are required Currently, the CTE mismatch between Si chip and substrate and assembly yield of such fine pitch interconnections serves as the biggest bottle neck issue In this work a simple copper column based bed of nails-wafer level interconnects showing greater potentials in meeting some of these requirements for next-generation packaging is reported The process development of fabricating the copper columns with various height and solder deposition on to the tip of the column is reported This technology has been developed to meet fine pitch of 100 microns and high density interconnections The development of a test chip demonstrator of 10 /spl times/ 10mm/sup 2/ with 3338 I/Os designed and fabricated for optimizing the process and the board level reliability test with out underfill performed under temperature cycling at range of -40/spl deg/C to 100/spl deg/C are also presented

High performance polymer/AlN composites for electronic substrate application

Abstract: An ideal high performance poly(etheretherketone) (PEEK)/AlN composite that has unique combination of anisotropic linear coefficient of thermal expansion (CTE) and dielectric properties was developed for the use in electronic packaging substrate as an alternative of conventionally used epoxy/E-glass substrate. The out-of-plane and in-plane CTEs of the composites were very close to that of copper and silicon chip, respectively. The dielectric constants of the composites are almost independent with increasing frequency. The dissipation factor decreased approximately 50% compared to the pure PEEK. These results reveal that the composite may be the futuristic candidate for high performance electronic packaging substrate.

Module with bumps for connection and support

Abstract: An electronic packaging module for inverted bonding of electronic devicss including semiconductor devices, integrated circuits, application specific integrated circuits, electomechanical devices and MEMS is produced with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of electronic devices. The input/output pads of the devices may be simultaneously bonded to the protuberances of the packaging module.

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

Abstract: High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.