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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


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Patent
15 Sep 2010
TL;DR: In this paper, a high heat-conducting copper-based composite material and a preparation method belonging to the technical field of electronic packaging materials are described. But the preparation method is not described.
Abstract: The invention relates to a high heat-conducting copper-based composite material and a preparation method thereof, belonging to the technical field of electronic packaging materials. The copper-based composite material consists of 50-80 percent by volume of electroplated diamond particles and 20-50 percent by volume of copper. The electroplated diamond particles and a caking agent are mixed according to the volume ratio of 1:1-4:1 and are produced into a diamond prefabricated part by using an injection forming process of the prefabricated part; and a copper matrix is directly placed on the diamond prefabricated part or is melt and poured on the diamond prefabricated part to be produced into the high heat-conducting copper-based composite material by using a pressure infiltration process. The copper-based composite material has higher heat conductivity ratio than that of an aluminum-based composite material; by plating the surface of diamond, the interface bonding of the matrix copper and the diamond can be improved and the interface heat resistance can be reduced; in addition, the material has low density and small thermal expansion coefficient and meets the requirement for light quality of packaging materials.

21 citations

Proceedings ArticleDOI
21 May 1995
TL;DR: In this article, the authors describe an effort in developing low-cost optoelectronic packaging and interconnect technologies for board-level optical interconnect applications, which includes hybrid packaging of electrical and optical components, e.g., vertical-cavity surface-emitting-laser (VCSEL) devices using a thin-film embedded-chip MCM technology.
Abstract: In this paper, we describe an effort in developing low-cost optoelectronic packaging and interconnect technologies for board-level optical interconnect applications. Specifically, our work includes (a) hybrid packaging of electrical and optical components, e.g., vertical-cavity surface-emitting-laser (VCSEL) devices using a thin-film embedded-chip MCM technology, (b) fabrication of optical polymer waveguides for board-level interconnect using standard planar processes, and (c) use of an adaptive interconnect process for waveguide patterning to accommodate alignment between optical device and waveguides. Our approach attempts to employ planar fabrication processes widely used in IC manufacturing and the existing packaging technology already developed in the electronic industry to optoelectronic packaging and interconnect for board-level applications. Our goal is to reduce both recurring and nonrecurring costs for the optical interconnect technology insertion.

21 citations

Journal ArticleDOI
TL;DR: In this paper, the specific temperature profile of a laser soldering process is investigated using a high power diode laser (HPDL) and the diffusion of the tin-based filler material through the nickel barrier using the information extracted from the temperature simulations.

21 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical closed-form solution for ply-level sublaminate analysis is investigated, where each layer is treated as a beam-type plate with orthotropic material properties.
Abstract: An accurate estimate of thermal stresses in multilayered microelectronics struc along the bonded interfaces is crucial for design and prediction of delamination-rel failures. Compared with a numerical method, analytical closed-form solution offer a more rapid method to obtain the stresses at the interfaces. An analytical m for ply-level sub-laminate analysis is investigated in this paper. The theory prese treats each layer as a beam-type plate with orthotropic material properties. As an ample, the results are shown for a three-layer beam problem with special orthotr material properties. Analytical model results are compared with the finite element ana results, as a first order approximation. @DOI: 10.1115/1.1535446 #

21 citations

Proceedings ArticleDOI
06 Nov 2009
TL;DR: In this article, a pre-process Chipfilm and a post-process Pick, Crack&Place (PCP&P) process is used for fabricating ultra-thin chips.
Abstract: Ultra-thin chip technology is identified as an enabler for overcoming bottlenecks in microelectronics, such as 3D integration, and for leading to new applications, such as hybrid, flexible system-in-foil (SiF). This, however, calls for new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. The application to SiF requires that the ultra-thin chips feature excellent mechanical reliability and flexibility. This paper focuses on a recently introduced novel technology, called Chipfilm™, for fabricating ultra-thin chips. The technology consists of a pre-process Chipfilm™ and a post-process Pick, Crack&Place™. Particular attention is paid to the design and characterization to the mechanical anchors that are broken in the Pick, Crack&Place process to singulate the thin chips. Also discussed is the characterization of the chip's mechanical stability and flexibility.

21 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896