Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

The rise of the 3rd dimension for system intergration

Abstract: Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP (`above' passivation), approach and a foundry level (`below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail

Materials and mechanics issues in flip-chip organic packaging

Abstract: The strength of flip chip organic packaging technology rests upon the knowledge and manufacturing base of C4 solder bump chip interconnection, and printed circuit technology infrastructure. The key innovation was the underfill encapsulation between the chip and the laminate which overcame the road-block of low cycle fatigue of C4 solder bump due to large CTE difference between silicon and laminate. The advent of SLC (surface laminar circuit) innovation extends the flip chip technology to higher solder bump density and larger chip I/O expected for future generations of semiconductors. The flip chip packages contain new materials, interfaces, and new processes which in turn govern the mechanical integrity of the packaging module and module card assembly. The increasing pervasiveness of electronic packages requires meeting new sets of environments. It is important to have a good understanding of materials, interface, metrology and mechanics issues related to organic packages, and how to apply this understanding in the modelling of design, process and reliability of flip chip. This paper will deliver an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers.

Method of forming a multilayer electronic packaging substrate with integral cooling channels

Abstract: Disclosed is an electronic packaging substrate which includes a sintered ceramic body having at least one internal layer of wiring and at least one cooling channel internal to and integral with the sintered ceramic body for cooling a heat-generating electronic device placed on the sintered body. Also disclosed is a method of making the electronic packaging substrate.

Inverted chip bonded module with high packaging efficiency

Abstract: An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of semiconductor devices The input/output pads of the semiconductor devices are simultaneously bonded to the protuberances of the packaging module

Thermal management in semiconductor device packaging

Abstract: Thermal management at device level packaging involves efficient and cost-effective removal of dissipated thermal energy from the device to assure its reliable performance over the long term. In the context of very high levels of integration of future ICs, thermal management will mean making such devices possible close to the natural limits set by thermal physics. This paper will present trends in important parameters and discuss solutions through examples.