Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

MicroSMD : A wafer level chip scale package

Abstract: This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

Abstract: A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W−1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than −10 dB from 8 GHz to 14 GHz.

Transient Frequency-Domain Thermal Measurements With Applications to Electronic Packaging

Abstract: Non-uniform power distribution, increased die-size, and multiple-chip modules present new challenges for the thermal management of modern integrated circuit (IC) packages. Thermal characterization techniques capable of resolving partial thermal resistances at the component level have received increased emphasis in development of advanced packaging technologies. This paper aims to develop a practical method for thermal characterization of IC packages using the frequency-domain measurement technique as a complementary technique to the widely used time-domain thermal transient measurement technique. This paper discusses practical implementation of the technique and demonstrates both thermal modeling and experimental results. Thermal impedances measured in frequency-domain yield the structure function, which describes the dynamic thermal response of the device based on thermal RC network analysis. Various applications of this technique in thermal characterization of the IC packages subjected to field conditions are also discussed.

Thermally induced stresses resulting from coefficient of thermal expansion differentials between an LED sub-mount material and various mounting substrates

Abstract: A study has been conducted to determine the effects of mechanical stresses induced from the coefficient of thermal expansion (CTE) differential between a light emitting diode (LED) chip, and various substrate materials to which the LEDs were mounted. The LEDs were bonded to typical packaging materials including ceramics, copper and metal matrix composites. The objective of this investigation was to determine the viability of implementing alternate substrate materials for packaging of LED power chips. In particular, thermally induced stresses resulting from the CTE differentials between the alternate substrate materials and the LED sub-mount material were analyzed and compared against the stresses resulting from the nearly ideal CTE match that is realized with traditional ceramic substrates.