scispace - formally typeset
Search or ask a question
Topic

Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
More filters
Book
31 Mar 1995

111 citations

Journal ArticleDOI
01 Apr 1997
TL;DR: Fully integrated microinductors and microtransformers based on two different geometries and ferrite composite materials are designed, fabricated, tested, and compared as discussed by the authors, and are deposited at low temperature, making them compatible with organic electronic packaging substrates.
Abstract: Fully integrated microinductors and microtransformers based on two different geometries and ferrite composite materials are designed, fabricated, tested, and compared. These devices are based on screen printed polymer/ferrite composites and electroplated copper coils, and are deposited at low temperature, making them compatible with organic electronic packaging substrates.

111 citations

Reference BookDOI
27 Sep 2000
TL;DR: In this article, thermal design of electronic equipment, thermal design for electronic equipment and its application in the field of computer networks, is discussed, where the authors propose a thermal design approach for computer networks.
Abstract: Thermal design of electronic equipment , Thermal design of electronic equipment , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

109 citations

Book
30 Sep 1989
TL;DR: In this paper, the authors review and discuss some important applications of polymers in electronics, including resist materials for integrated circuit fabrication, polyimides as electronics packaging materials, and polymers as integrated circuits encapsulates.
Abstract: The object of this book is to review and to discuss some important applications of polymers in electronics. The first three chapters discuss the current primary applications of polymers in semiconductor device manufacturing: polymers as resist materials for integrated circuit fabrication, polyimides as electronics packaging materials, and polymers as integrated circuits encapsulates.

108 citations

Journal ArticleDOI
TL;DR: In this paper, the impact of thin film residual stresses has been studied at both wafer level and package level for flip-chip die attach process, and two solutions have been suggested to prevent catastrophic delamination in copper/low-k flipchip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low k structures to reduce possible area for crack growth.
Abstract: Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

105 citations


Network Information
Related Topics (5)
Wafer
118K papers, 1.1M citations
85% related
Integrated circuit
82.7K papers, 1M citations
84% related
Transistor
138K papers, 1.4M citations
79% related
CMOS
81.3K papers, 1.1M citations
78% related
Silicon
196K papers, 3M citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896