Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Photonics challenge to electronic packaging

Abstract: Photonics packaging is a challenge to electronic packaging for two important reasons. The first and most obvious is that light must have access to the device. There must be a window, port or optical fiber interface. The other and more serious problem is that most devices require a highly controlled atmosphere. And if having to accommodate both electrons and photons were not enough, innovators have added mechanical motion to optical devices. Micro-opto-electro-mechanical systems (MOEMS) bring photonics, electronics, optics, physics and mechanical engineering together on one semiconductor device. This appears to be the ultimate convergence of technology domains and can also include biology and chemistry.

NASA Electronic Parts and Packaging Program

Abstract: NEPP program objectives are to: (1) Access the reliability of newly available electronic parts and packaging technologies for usage on NASA projects through validations, assessments, and characterizations, and the development of test methods/tools; (2)Expedite infusion paths for advanced (emerging) electronic parts and packaging technologies by evaluations of readiness for manufacturability and project usage consideration; (3) Provide NASA projects with technology selection, application, and validation guidelines for electronic parts and packaging hardware and processes; nd (4) Retain and disseminate electronic parts and packaging quality assurance, reliability validations, tools, and availability information to the NASA community.

Packaging of large and low-pitch size 2D ultrasonic transducer arrays

Abstract: The successful packaging and electronics integration of large 2D array devices with small pitch-sizes, such as fully populated 2D ultrasonic transducer arrays, require a flexible, simple, and reliable integration approach. One example for such electronics integration is based on through silicon vias (TSVs) with under-bump metallization (UBM) stack for solder bumping. In this paper, we demonstrate such an approach by successfully integrating a fully populated 2D ultrasonic transducer array. Our integration is based on a previously reported TSV technology (trench-frame technology), based on trench-isolated interconnects with supporting frame. We successfully combined the trench-frame technology with a simple UBM preparation technique - electro plating or chemical plating techniques with passivation layers for UBM pad definition are not required. Our results show high shear strength (26.5g) of the UBM, which is essential for successful flip-chip bonding. The yield of the interconnections is 100% with excellent solder-ball-height uniformity (σ = 0.9 µm). As demonstrated in this paper, this allows for a large-scale assembly of a tiled array by using an interposer. A design guideline for finer element-pitch design was developed suggesting that fusion bonding strength and the length of pillars are the main design parameters.

Thermal Interface Materials in Electronic Packaging

Abstract: With the continual increase in cooling demand for electronic packaging, there has been an increased focus within the microelectronics industry on developing high performance thermal solutions. Thermal interface materials (TIMs) play a key role in thermally connecting various components of the thermal solution. As electronic assemblies become more compact and there is an increase in processing bandwidth, escalating thermal energy has become more difficult to manage. The major limitation has been nonmetallic joining using poor TIMs. The interfacial, versus bulk, thermal conductivity of an adhesive is the major loss mechanism and normally accounts for an order magnitude loss in conductivity per equivalent thickness. The next generation TIM requires a sophisticated understanding of material and surface sciences, heat transport at submicron scales, and the manufacturing processes used in packaging of microelectronics and other target applications. Only when this relationship between bond line manufacturing processes, structure, and contact resistance is well understood on a fundamental level, will it be possible to enhance interfacial thermal conductance and advance the development of miniaturized microsystems. TIMs are widely needed to improve thermal contacts for facilitating heat transfer in electronic packaging, such as that associated with the flow of heat from a microprocessor to a heat spreader or a heat sink in a computer. A TIM is commonly in the form of paste, solder, or a resilient sheet that serves to fill a gap between the two adjoining surfaces. The resiliency helps the conformability. The performance of a TIM is enhanced by conformability of the interface material to the topography of the mating surfaces because the air residing in the valleys in the surface topography is thermally insulating and should be displaced by the interface material. This chapter will discuss interfacial conduct mechanism and review current status and future trends of commercial and advanced TIMs, including metallic, organic, graphite, hybrid, and nanotechnology-based TIMs.