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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors explored the use of an invar alloy for the low CTE phase of a composite plate in order to allow the formation of a passivation layer protecting from reaction with liquid Al during squeeze casting, the honeycomb is made of the Cr-rich alloy commonly called Stainless-invar.

17 citations

Patent
30 Jun 1993
TL;DR: In this paper, a potted plant is sorted according to a grade, placed in a decorative cover, and then automatically deposited into a protective sleeve, ready for containment within a shipping carton.
Abstract: The present invention is a modular system for packaging articles for shipment. In particular, a potted plant is sorted according to a grade, placed in a decorative cover, then automatically deposited into a protective sleeve. The potted plant thus packaged is ready for containment within a shipping carton. Various components of the system may be adapted for various packaging needs and circumstances.

17 citations

Proceedings ArticleDOI
15 Apr 2012
TL;DR: In this paper, a methodology consisting of an experimental approach with the support of FEM modeling is presented for experimental characterization of Chip-Package Interaction (CPI) effects during 3D assembly steps: stacking and packaging.
Abstract: FET arrays are investigated from the viewpoint of Chip-Package Interaction (CPI) sensor suitability and presented as a possible solution for experimental characterization of CPI effects during 3D assembly steps: Stacking and packaging. The study presents a methodology consisting of an experimental approach with the support of FEM modeling. The use of the transistors as stress sensors covering in-plane stress components is justified, after which the applicability of the transistors to the actual stacking and packaging stress states is discussed. Calibration to in-plane stress of long and short channel transistors, p and n type, is performed to obtain sensor sensitivities and link stress to current shift by according calculated piezocoefficients. Testing the FET arrays as sensors is firstly done by means of a simple structure where a die is glued to a plastic substrate. The electrical measurements are compared to FEM models and profilometric scans. The sensors are next utilized to obtain first results from 3D stacking and packaging. The underfill - microbump mechanism in a 2-die stack is quantified and initial results on overmould impact are discussed.

17 citations

Proceedings ArticleDOI
05 Jul 2012
TL;DR: A new testing method is presented which allows maximum mode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure.
Abstract: This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximummode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut fromreal devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for delamination testing in electronic packaging.

17 citations

Journal ArticleDOI
TL;DR: In this article, a unique vacuum printing encapsulation system (VPES) was developed to solve such problems with lower cost than transfer molding, which used matrix type BGA and chip scale package (CSP) for this test.
Abstract: Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology.

17 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896