Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Modeling transient thermal response of pulsed power electronic packages

Abstract: Steady-state power conversion applications have benefited from numerous packaging and cooling improvements, and there has been a push to apply the same techniques to pulsed power electronic systems and devices. However, the unique aspects of pulsed systems create a trade-off between high package thermal capacity for mitigating rapid temperature rise and low thermal resistance for rapid heat rejection. This report details a numerical study of several electronics packages with varying levels of cooling integration. Using Finite Element equivalent thermal circuit models to perform transient simulations of the packages, the effect of convective improvement and a reduced thermal path upon junction temperature response was examined. Results showed that while a reduced thermal stack and high convection rate speeds the return to steady state after a pulse, the ability for improved convection to mitigate junction temperature rise diminishes significantly as pulse widths approach the thermal time constant of the package. In addition, the reduced thermal capacity of the integrated packages causes them to exhibit higher junction temperature rise and larger temperature swings than basic, non-integrated packages for certain pulse conditions. The worst case examined showed a direct die-cooling package exhibit a 3x increase in peak temperature and a 5x increase in pulse-to-pulse temperature swing over a standard, non-integrated package.

Advanced Package Prototyping Using Nano-Particle Silver Printed Interconnects

Abstract: To reduce manufacturing cost, lead time, and process complexity, an embedded-active approach that targets rapid prototyping and low-volume production in micro-system packaging is being developed. The approach involves a rapid prototyping of micro-system packaging by a data-driven chip-first packaging process using direct printing of nano-particle metals. In the chip-first process, bare dice are first embedded into a copper or stainless steel carrier substrate, fixed by filling the gap between the chips and the substrate with thermoplastic adhesives, and planarized to a common planar surface. On the coplanar substrate, polyimide film is laminated to form a dielectric layer. Through the dielectric layer to the chip metal pads, micro vias are drilled by laser ablation. The vias are filled with nano-particle silver (NPS). The NPS is deposited by screen printing or aerosol-jet printing and an electrical circuit is formed. This packaging approach is a dry process and it does not require any photo masks for circuit patterning, resulting in reducing packaging turn-around time from months to days. It is also less limited by substrate composition and morphology, eliminates the need for special chip processing such as flip chip solder bumps, and permits using any chip technology and any chip supplier allowing mixed devices. The embedded-active process with NPS avoids the extreme processing conditions required for standard IC fabrication such as wet chemistry processing and vacuum sputtering. The NPS can be sintered at plastic-compatible temperatures as low as 230?C to form material nearly indistinguishable from the bulk metal. The embedded-active packaging shows good reliability performance in terms of thermal shock, which is performed in the range of -40?C and 125?C. These results represent an important step to a system packaging characterized by high-density, low-cost, and data-driven fabrication for rapid package prototyping. This paper presents details of the rapid prototyping process sequence, an initial reliability characterization of the package architecture, and a failure mode analysis of the packages.

Assembly of planar array components using anisotropic conducting adhesives-a benchmark study: pt.I. Experiment

Abstract: This paper presents new results from an experimental and theoretical program to evaluate relevant process parameters in the assembly of a 500 /spl mu/m pitch area array component using anisotropic conductive adhesive (ACA) materials. This experimental configuration has features of micro ball grid array (/spl mu/BGA), chip scale packaging (CSP), and also flip-chip and conventional ball grid array (BGA) package structures. A range of materials combinations have been evaluated, including (random filled) adhesive materials based on both thermoplastic and thermosetting resin systems, combined with both organic and thick-film on ceramic substrate materials. The ACAs used have all been applied as films, and hence are also known as anisotropic conducting films (ACF). The test assemblies have been constructed using a specially developed instrumented assembly system which allows the measurement of the process temperatures and pressures and the consequent bondline thickness reduction and conductivity development. The effects of the process parameters on the resulting properties, particularly conductivity and yield, are reported, A complementary paper indicates the results of computational fluid dynamics (CFD) models of the early stages of the assembly process which allow the extrapolation of the present results to finer pitch geometries.

Method for synthesizing phosphorus-containing polyester for fire retardant electronic packaging material

Abstract: The invention relates to a method for synthesizing phosphorous polyester used for fire-retardant electronic packaging materials, aiming to obtain the polyester with high fire resistance to solve the fire-retardant problem of the electronic packaging materials The method for synthesizing the phosphorous polyester comprises the following steps that: firstly, polylol is added into a four-mouth flask, and the temperature is increased to over 100 DEG C so that the polylol is stirred to be melt; secondly, polyatomic acid/ estolide, reactive phosphorous compound and catalyst are respectively added into the molten polylol; the esterification reaction begins and esterifying water is generated and distilled off; thirdly, vacuum-pumping is performed for polycondensation when the esterification rate reaches over 95 percent; fourthly, end capping reagent is added and then the finished phosphorous polyester can be prepared, wherein, the acid value range is between 50 and 250 KOH/g, and the fusing temperature range is between 60 and 130 DEG C The phosphorous polyester prepared by the method is used for the fire-retardant electronic packaging materials and can realize non-halogenation of the electronic packaging materials

Via metallization for A1N ceramic electronic package

Abstract: Metallization formulations containing a mixture of AlN and metal are used to form hermetic vias in AlN dielectric bases for electronic packaging. The metal may be W, Mo, or mixtures thereof. The metallization may be cofired with the AlN dielectric base. The metallization is especially useful for making electrically conductive hermetic through-vias in AlN bases.