Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Microwave packaging of optoelectronic components

Abstract: The design and performance characteristics of single-mode fiber-coupled laser and photodiode packages suitable for use in microwave RF or broadband transmission systems are discussed. The necessary packaging considerations to achieve laser and photodiode performance to 20 GHz are described. Mechanical, thermal, optical and microwave details of two laser packages and one photodiode package are given, and the optoelectronic characteristics of the packaged units are presented and discussed. It is shown that the intrinsic optoelectronic performance of the components is preserved to at least 20 GHz and that this performance is not affected by package design. >

Development of SiC power devices and modules for automotive motor drive use

Abstract: SiC Power devices are expected to greatly improve the efficiencies and operating capabilities of next generation electric and hybrid electric vehicles. The use of these devices allows for drastic size and weight reduction at the module and system levels of motor drives used in automotive applications. A new SiC MOSFET structure with both gate and source trenches is presented. This greatly reduces device on-resistance while preventing oxide destruction at the gate trench bottoms. Finally new packaging methods under development are outlined that take advantage of the benefits these new devices have to offer by transfer molding them in a high temperature resistant epoxy resin. This leads to modules with low thermal resistance and high power density that, when configured as a three phase inverter, reduce total system footprint and parasitic inductance.

Single level integrated packaging modules for high performance electronic systems

Abstract: In this paper, we studied a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies toward single level integration. This new approach is an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Main benefits include very high performance, ultra high density, mixed-signal integration, and inexpensive. Several key technologies such as chip assembly and planarization were developed. A feasible fabrication procedure for single level integration has been established. Demonstrating modules were presented. Interconnect structures, signal and power distribution, and electrical performance were studied theoretically and experimentally for GHz off-chip operating. Properties of signal propagation and coupling from chip to chip were investigated both in frequency domain and in time domain by simulations and by high frequency measurements. The studies show that the new modules are capable of several Gb/s/pin data rate for off-chip communications. Besides, some design guidelines for best performance are obtained through the work.

A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model

Abstract: As CMOS technology scales to nanometer regime, power dissipation issues and associated thermal problems have emerged as critical design concerns in most high-performance integrated circuits (ICs) including microprocessors. In this scenario, accurate estimation of the silicon junction (substrate or die) temperature is crucial for various performance analyses and chip-level thermal management. This paper introduces the notion of self-consistency in the junction temperature estimation by taking into account various electrothermal couplings between chip power, average junction temperature, operating frequency, and supply voltage. The self-consistent solutions of the average junction temperature are shown to have significant implications for various chip-level power, performance, reliability, and cooling cost tradeoffs. Moreover, a realistic package thermal model is introduced that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The model is subsequently incorporated in the self-consistent substrate thermal profile estimation, which is discussed in Part II with implications for power estimation and thermal management in nanometer-scale CMOS technologies.

Predicted stresses in ball-grid-array (BGA) and column-grid-array (CGA) interconnections in a mirror-like package design

Abstract: There is an obvious incentive for using bow-free (temperature change insensitive) assemblies in various areas of engineering, including electron device and electronic packaging fields. The induced stresses in a bow-free assembly could be, however, rather high, considerably higher than in an assembly, whose bow is not restricted. The simplest and trivial case of a bow-free assembly is a tri-component body, in which the inner component is sandwiched between two identical outer components (“mirror” structure), is addressed in our analysis, and a simple and physically meaningful analytical stress model is suggested. It is concluded that if acceptable stresses (below yield stress of the solder material) are achievable, a mirror (bow-free, temperature-change-insensitive) design should be preferred, because it results in an operationally stable performance of the system.