Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Study on flip chip assembly of high density micro-LED array

Abstract: Flip chip assembly technology is an attractive solution for high I/O density and fine-pitch microelectronics packaging. Recently, high efficient GaN-based light-emitting diodes (LEDs) have undergone a rapid development and flip chip bonding has been widely applied to fabricate high-brightness GaN micro-LED arrays [1]. The flip chip GaN LED has some advantages over the traditional top-emission LED, including improved current spreading, higher light extraction efficiency, better thermal dissipation capability and the potential of further optical component integration [2, 3]. With the advantages of flip chip assembly, micro-LED (μLED) arrays with high I/O density can be performed with improved luminous efficiency than conventional p-side-up micro-LED arrays and are suitable for many potential applications, such as micro-displays, bio-photonics and visible light communications (VLC), etc. In particular, μLED array based selif-emissive micro-display has the promising to achieve high brightness and contrast, reliability, long-life and compactness, which conventional micro-displays like LCD, OLED, etc, cannot compete with. In this study, GaN micro-LED array device with flip chip assembly package process was presented. The bonding quality of flip chip high density micro-LED array is tested by daisy chain test. The p-n junction tests of the devices are measured for electrical characteristics. The illumination condition of each micro-diode pixel was examined under a forward bias. Failure mode analysis was performed using cross sectioning and scanning electron microscopy (SEM). Finally, the fully packaged micro-LED array device is demonstrated as a prototype of dice projector system.

Enhancing the electrical insulation of highly thermally conductive carbon fiber powders by SiC ceramic coating for efficient thermal interface materials

Abstract: Mesophase pitch-based carbon fibers (MPCFs), which have ultrahigh intrinsic thermal conductivity and one-dimensional morphology with high-aspect ratios, can act as excellent fillers for improving the oriented heat dissipation rate of thermal interface materials (TIMs). However, the high electrical conductivity hinders their application in some electronic packaging fields. Herein, a SiC ceramic layer is uniformly and firmly coated on the surface of the powder-like MPCFs by a dynamic chemical vapor deposition method to obtain the high thermal conductivity and suitable electrical insulation. The ceramic coating layer exhibits a porous structure, complete encapsulation and adjustable thickness in the range of 90–600 nm. Employed as the thermal conductive fillers, the SiC-coated MPCF-derived TIMs exhibit comparable thermal conductivity and significantly enhanced electrical insulation performance compared with that from original carbon fiber. For instance, the pad prepared from the coated carbon fiber with a medium coating thickness of 200 nm shows a high through-plane thermal conductivity of 12.8 W m−1 K−1, high electrical resistivity of 3.4 × 1010 Ω cm and satisfactory breakdown voltage value of 1100 V mm−1. This work opens a new avenue to integrate the thermal conductivity and electrical insulation of carbon materials as thermal conductive fillers for electronic packaging.

Conductivity improvement of microstructures made by nano-size-silver filled formulations

Abstract: The most important problems connected with R&D work for microelectronic industry are miniaturization all electronic devices and ready equipment. This trend has no other options especially on the telecommunication, computers, advanced microelectronics and military fields. Those current trends are giving quite new requirements for all R&D teams, especially those, which are creating new technology, new materials and production methods. Right now is generally well known that Ink-Jet technology offers very new possibilities for production much better packaging circuits. Also is clear that for this purpose is a wide selection of several type materials with different functions (conductance, resistance, etc.). Of course Ink Jet method creates many new requirements not only for technology and production equipment, but mostly for materials which will be used. As example dispensing speed is as high as up to 2000 dots/sec, and such dispensing parameters create quite strong limitations connected with properties of dispensed medium - especially viscosity which should be less than 60 mPas. During each "shoot" very high acceleration is created up to 105 g. Within a few microseconds drop velocity variation up to 10 m/s occurs. This phenomenon requires the highest uniformity for dispensed medium. The Ink-Jet technology is used year by year wider for microelectronic packaging [1,2] and areas for printing very low pitch matrix (e.g. very fine pitch paths, antennas) seem to be extremely attractive. But there are special demands for ink-jet printing materials. The most important, as we've mentioned, is very low viscosity value and especially highly homogenous structure (like molecular fluid parameters) to avoid sedimentation and separation during dispensing process. Additionally, for electrical conductivity of printed structure, the liquid has to contain a number of percentage conductive filler with nano-sized dimension to avoid the printing nozzle blocking. The nano-size silver seems to be one of the best candidates for this purpose, especially when it's particle size dimensions will be less than 10 nm. It is important to remember, that silver atom size has diameter 0.28 nm, so such a small filler particle is comparable with size of binder fluid molecule. This is classical situation when formula will has stable properties.

Coupled Thermal-Stress Analysis for FC-BGA Packaging Reliability Design

Abstract: In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stress distributions of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distributions. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a flip-chip ball grid array package under field conditions. It was found that: 1) the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to the average contact thermal resistance in the case of uniform contact pressure, and 2) the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation under field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design. It was found that the sensitivity of uncertain variables and the thermal fatigue life distribution of solder joints could change significantly depending on a combination of factors concerning the failure sites of solder bumps and the boundary conditions of the motherboard.