Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Active Thermal Control of Distributed Parameter Systems With Application to Testing of Packaged IC Devices

Abstract: Active control of the die-level temperature is desirable during production testing of high power microprocessors, so as to ensure accurate performance classification. Such control requires that the controlling thermal load time-lead the dissipated thermal load and that it be modulated to account for the distributed thermal capacitance and resistance of the device packaging. The analysis in this paper demonstrates fundamental limits of temperature control for typical devices under test conditions. These limits are identified for specified control power to die power ratios. The effects of test sequence design and device package design on the temperature control limits are also examined. The theory developed can be applied to any thermal control problem where a conductive medium separates the control source from the location where control is desired.

Modular electronics packaging system

Abstract: A modular electronics packaging system includes multiple packaging slices that are mounted horizontally to a base structure. The slices interlock to provide added structural support. Each packaging slice includes a rigid and thermally conductive housing having four side walls that together form a cavity to house an electronic circuit. The chamber is enclosed on one end by an end wall, or web, that isolates the electronic circuit from a circuit in an adjacent packaging slice. The web also provides a thermal path between the electronic circuit and the base structure. Each slice also includes a mounting bracket that connects the packaging slice to the base structure. Four guide pins protrude from the slice into four corresponding receptacles in an adjacent slice. A locking element, such as a set screw, protrudes into each receptacle and interlocks with the corresponding guide pin. A conduit is formed in the slice to allow electrical connection to the electronic circuit.

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Abstract: Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm2 without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing

Packaging technologies for RFICs: current status and future trends

Abstract: In the current wireless market, competitive pressures are driving the electrical performance of RF integrated circuit (RFIC) devices to new levels. At the same time, the demands placed on packaging of these RFICs have caused more resources to be focused on solutions. The result has been that high frequency packaging is called upon to provide low cost, thermally efficient, miniaturized products for a wide range of wireless telecommunications applications. The packaging of RFICs covers a wide range of technologies, with a number showing promise for future developments. The end applications for these packaged devices range from fixed base systems to high portability, handheld uses. Both types require that aggressive performance and economic consideration be paid to packaging technique. The dominant package options are the single chip plastic encapsulated RFIC and its cousin, the ceramic package. Advanced package technologies include the many forms of multiple chip modules (MCM), leadless array packaging (including ball grid array (BGA) and near-chip scale pages), as well as thermally enhanced packaging in ceramic and laminate substrate materials. In looking ahead to the next generations of packages, a key determinant lies on the road to advanced packaging for RFICs. System level integration and manufacturing technology for wireless products will likely remain primarily surface mount technology (SMT). With this constraint; smaller, higher levels of device integration, increased thermal capability and integration will place increased burdens on packaging technology. Some insights into potential emerging technologies and their enabling requirements will be offered.