Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

New packaging of a chip on a board by a unique printing method

Abstract: Transfer molding is a typical method for packaging integrated circuits (ICs). Transfer molding is very difficult to do at heights less than 1 mm, and has a limited surface mounting area. Recent research of high density surface mounting for thinner and lighter weight packaging has progressed for both IC cards and liquid crystal displays (LCDs). However, the dispensing method has many problems, such as the height variations of the coating, difficulties of uniform spreading on large size ICs, and one-by-one encapsulation. A unique printing method is developed to solve such problems. Through this method it is possible to achieve a height less than 1 mm and a uniform thickness on an integrated system. On reaching these parameters, the surface mount ICs replace molded packaged devices that are manufactured using expensive equipment and molding dies. The method requires only a small amount of epoxy resin and is, therefore, more economical than the conventional transfer molding process. A one-component epoxy resin NPR-150 suitable for printing is developed. >

Cost-effective manufacturing of aluminium silicon carbide (AlSiC) electronic packages

Abstract: Current microelectronics places ever increasing demands on the performance of electronic packaging materials and systems in terms of thermal management, weight, and functionality requirements. These requirements have pushed the development of new materials and processing technologies to provide high performance packaging solutions cost-effectively. Aluminum silicon carbide (AlSiC) metal matrix composite (MMC) packages have a unique set of material properties that are ideally suited to the above requirements. The AlSiC coefficient of thermal expansion (CTE) value is compatible with direct IC device attachment, allowing for the maximum thermal dissipation into the high thermal conductivity (170-200 W/mK) AlSiC package. Additionally, the low material density of AlSiC (3 g/cm/sup 3/) makes it ideal for weight sensitive applications. The Ceramics Process Systems (CPS) AlSiC fabrication and processing technology provides both the material and the net-shape functional packaging geometry in one process step. This processing technology also allows the Concurrent Integration/sup TM/ of feedthroughs, seal rings and substrates, which eliminates the need for additional assembly operations. These manufacturing attributes allow AlSiC packaging to be cost competitive and offer performance advantages over competing packaging products/systems. The AlSiC packaging design process and manufacturing process is outlined through actual product examples.

Full-Field 3-D Flip-Chip Solder Bumps Measurement Using DLP-Based Phase Shifting Technique

Abstract: The flip chip, a type of chip mounting used in semiconductor devices, has become one of the most popular innovations in the semiconductor packaging industry. The height of flip-chip solder bumps ranges from 20 to 140 mum with a required measurement accuracy of 2 mu m. Three-dimensional (3-D) measurement of flip-chip solder bumps is crucial to flip-chip manufacturing quality and process control. Currently, 3-D measurement systems for flip-chip solder bumps are mainly based on laser scanning techniques. However, they require a high implementation cost, and suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for flip-chip solder bumps is proposed. The proposed system is based on a phase shift technique, in which the phase is accurately shifted by a software-controlled grating using a digital light processing (DLP) unit that allows full-field measurement of a projected flip chip. The DLP unit can provide a higher fringe-contrast pattern at a faster changing time than a liquid crystal display (LCD) panel. Phase shift-based measurement systems require a calibrated system parameter, which is generally considered a fixed value in currently available methods. In this paper, adaptive parameter values, instead of a fixed value, are used to improve measurement accuracy. The proposed system also adopts a fringe-contrast thresholding to solve the pseudo-surface height problem for high reflective solder bumps and low reflective substrate in a flip chip. Experiments have shown that the 3-D measurement of flip-chip solder bumps is very efficient and effective with the proposed system. Computation time of the proposed 3-D measurement system for a 640 x 480 image that contains almost 500 solder bumps is less than 1 s, and measurement accuracy meets the required specification of 2 mum.

Packaging of MEMS devices

Abstract: This paper examines issues in the packaging of silicon-micromachined devices. Standard microelectonics packaging seeks to physically isolate the integrated circuits from harmful elements in the environment, to provide mechanical strength for the die, to facilitate thermal dissipation, and to sustain electrical communication with outside circuits. However, due to the many novel applications of MEMS devices, new sets of packaging requirements need to be met and further research on packaging technology to meet non-traditional requirements are needed.

Fluid delivery systems for electronic device manufacture

Abstract: The present invention relates to new methods for delivering solutions during electronic device manufacture. Methods of the invention include delivering metallization solutions to the device at an angle of less than 90 degrees with the surface of the device. The method may further comprise partially treating the device by delivering the metallization solutions from above the device, turning the device over, and then completing treatment by delivering the metallization solutions from below the article. The method is particularly useful in the formation of printed circuit boards and other electronic packaging devices having through-holes and blind vias.