Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Simulation of Migration Effects in Solder Bumps

Abstract: Due to miniaturization, the width of interconnects, as well as the dimensions of solder bumps, decreases. As a result of the finer pitch, the density of solder bumps in flip-chip designs increases. This allows the usage of small 3-D assembly technologies like package-on-package in compact applications. The reduction of the geometrical dimensions leads to an increase of the carried current density in the solder bumps. Due to the device design rules, the current flowing through such a solder bump in flip-chip designs extends, for instance, from 0.2 to 0.4 A. The geometry of the solder bump and the trace leads to current density distributions with high local concentrations, which are known as current crowding (CC). CC is occurring at the contact between the trace and the solder bump, as well as in discontinuities of the traces like vias, etc. Due to CC migration, effects like electro- and thermomigration become critical reliability problems in such assembly technologies [3], [4], [19], [20]. Under high dc current density conditions, electromigration in the solder joint is known as a reliability concern for high-density flip-chip packaging and power packaging [8]. This paper will give an overview of thermal-electrical and mechanical finite-element simulations of migration effects in solder bumps and related assembly technologies. The effects will be illustrated by some simulation examples.

Design, Fabrication, and Calibration of a Piezoresistive Stress Sensor on SOI Wafers for Electronic Packaging Applications

Abstract: This paper presents the development of a piezoresistive stress sensor fabricated on silicon-on-insulator (SOI) wafers for measurement of electronic packaging stress at high temperature. The sensor consists of a series of sensor elements and calibration elements. The sensor elements comprise a 0deg-90deg p-type piezoresistor pair and a plusmn45deg n-type piezoresistor pair for stress measurement, and the calibration elements comprise two polar three-piezoresistor rosettes with specific angels to calibrate the piezoresistive coefficients. The sensor and the calibration piezoresistors are etched from the SOI layer as separate ldquosilicon islandsrdquo on the dielectric buried oxide (BOX) layer. This configuration exploits the excellent electrical insulation of the BOX layer, and enables high-temperature operation of the stress sensor by eliminating the leakage current. Design, fabrication, and the calibration of the piezoresistors at high temperatures show the feasibility of the SOI high-temperature stress sensor. The piezoresistive coefficients are calibrated versus stress and temperature, and the nonlinearity of the resistance versus temperature and the calibration errors are discussed in detail.

Printed circuit structures, the evolution of printed circuit boards

Abstract: The Printed Circuit Board (PCB) is the backbone of electronics and a large number of consumer devices. The challenge to put more function in a smaller space requires more components utilizing smaller bond pads, smaller lines and tighter pitch. The electronic packaging industry has aggressively pursued novel ways to shrink and stack multilayer boards inside smaller volumes. Industry is approaching serious obstacles in the continued size reduction requirements with the need for wires, epoxy, vias, solder and sometimes bolts and screws to mount the boards. The next logical step is to move beyond 2D stacking, which is 2.5D to make 3D packages and to utilize the 3 rd dimension directly. Eliminate the traditional 2D FR4 board and the wires, epoxies, vias and solder and make the next generation packages utilizing the 3 rd dimension; the Printed Circuit Structure (PCS). The PCS concept will allow passives, actives and even antennas to move out of the XY plane and into the XZ and YZ planes. This new dimension will appear to be very complex and next generation circuit optimization will be required, but the end result will net a significant improvement in volume utilization. In addition, if new materials are developed and utilized properly, the PCS will be the box or the package thus eliminating all the bolts and screws necessary to mount a PCB in a traditional box or package, thus again saving space and reducing weight. nScrypt and the University of Texas at El Paso will present 3D Printing of Printed Circuit Structures. A demonstration of true 3D electronic structures will be demonstrated and shown as well novel approaches which utilize Computer Aided Design (CAD) to 3D Printing which will include the electronics portion. Introduction Printed Circuit Boards are a critical component in almost every electronic device. Electronics come in a variety of shapes and sizes which is determined by function, environment and physical shape; at least the physical device comes in a variety of shapes. The electronics portion of the device is limited to a standard 2.5 D approach. This implies building a multilayer board with dimensions in X and Y and then mounting that board to a structure of specific shape and volume. But data transfer speeds are seeing their limitations in this conventional PCB approach. New materials are being used to overcome these limits, but the actual structure will need to see improvements too. 1,2 Wires, epoxy, vias, solder and connectors all contribute parasitic harmonic effects to standard PCBs due to impedance mismatching and/or sharp turns that create electromagnetic (EM) reflections. 3,4 Using 3D printing, there will no longer be a need for wires, epoxy, vias, solder or bolts and screws. The 3D printing process can move from building a circuit which is flexible enough to be rolled into a cylinder, to building a cylinder with a curved circuit within it. These structures will be solid or even porous depending on the applications of the PCS. 3D printing has been around since the 1980’s and starting as a novel demonstration, but is now becoming more ubiquitous. With the introduction of table top fused deposition manufacturing (FDM) machines even home users have the opportunity begin exploring possible 3D prints. These printers allow users to convert their CAD into physical structures for prototyping or even small part replacements. 5 3D Printing 3D printing or Additive Manufacturing (AM) is an efficient and green form of manufacturing which fabricates products by building successive layers of material, thus creating little to no waste. Traditional subtractive techniques start with bulk materials and machine away unwanted excess.The first concept of AM known as Selective Laser Sintering (SLS) places a thin layer of the powdered material onto a work surface and a laser beam patterns metal thin shapes by sintering the powder particles together. The work surface is lowered and a second layer of powder is spreadon top of the existing metal shape. Through multiple lowering’s, powder spreading and sintering cycles, a 3D structure can be built with features and voidsthat subtractive processes cannot achieve; resolution of lines are around 0.005in and layer thickness of 0.004in. StereolithographyApparatus (SLA) is another 3D printing approach which is a similar SLS but instead of sintering powder, it hardens photosensitive resin (liquid). There are some builds that require support structure materials if there are large gaps in the 3D structure during the build. Support structure materials are temporary and typically dissolved with water. SLA, like SLS, is an expensive process given the time it takes to build a part (minutes to hours) and the photosensitive resin is very expensive. The features created are solid and the surface finishes can be smooth; feature sizes can be as small as 0.001”per inch for commercial grade tools, but research tools have achieved 0.0001” features. Figure 1 are photos of commercial tools for 3D printing and Direct Printing.

Bond wireless multichip packaging technology for high-speed circuits

Abstract: A multichip packaging technology has been developed for use in the advanced hybrid integration of semiconductor chips made of different materials. The resulting multichip module (MCM) is similar to a monolithic circuit in that all the interconnects are made by photolithography and thin-film metallization. Any semiconductor chip can be integrated in this scheme without special chip metallization patterns or the incorporation of special features on the chips. In this technique, chips with backside contacts, such as laser diodes and photodetectors, can be packaged, offering greater flexibility and speed than other hybrid or multichip packaging technologies. Several different optoelectronic receivers which combine various GaAs, Si, and GaInAs chips have been successfully integrated and operated at frequencies ranging from 100 MHz to above 1 GHz. >

Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)

Abstract: Recently, wafer-level packaging (WLP) has become one of the promising packaging technologies due to its advantages, such as fewer processing steps, lower cost, and enhanced device performance compared to conventional single-chip packaging. Many developments on new WLP design, material, and process have been accomplished according to performance and reliability requirement of the devices to be packaged [1], [2]. For a lower cost, higher performance, and environmentally green packaging process, anisotropic conductive film (ACF) flip chip assembly has been widely used, such as in ultrafine-pitch flat panel display (FPD) and general semiconductor packaging applications, too. However, there has been no previous attempt on the wafer-level flip chip assembly using ACFs. In this paper, wafer-level flip chip packages using preapplied ACFs were investigated. After ACF prelamination on an electroplated Au bumped wafer, and subsequent singulation, singulated chips were flip-chip assembled on an organic substrate using a thermocompression bonding method. Au-plated bumps were well assembled on Ni/Au pads of organic substrates. The electrical, mechanical properties and the reliabilities of wafer-level flip chip assemblies (WL-FC As) were evaluated and compared with conventional ACF flip chip assemblies using the thermocompression method. Contact resistance measurement was performed after thermal cycling, high temperature/humidity, and pressure cooker test. ACF joints between electroplated Au bumps and substrate metal pads showed stable contact resistance of 5 mOmega per a bump, strong bump adhesion, and similar reliability behaviors compared with conventional ACF flip chip joints using a thermocompression bonding. As a summary, new wafer-level packages using preapplied ACFs were successfully demonstrated for flip chip assembly. The new wafer-level packages using preapplied ACFs can be widely used for many nonsolder flip chip assembly applications such as chip-on-board (COB), chip-on-flex (COF), and chip-on-glass (COG).