Topic
Electronic packaging
About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.
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TL;DR: In this article, a comprehensive finite element approach was introduced to model the moisture induced delamination in a stacked die package during solder reflow, which could reduce the users' effort in dealing with the multipleloading boundary conditions in the fracture mechanics finite element simulation.
15 citations
26 May 2009
TL;DR: The manufacturing of through silicon vias has been intensively studied in Advanced Packaging and starts industrial commercialization at the moment as discussed by the authors, which is widely considered as the next revolution for electronic packaging and hetero system integration.
Abstract: Beyond doubt through silicon vias (TSVs) will pave the way for 3D interconnects and therefore initiate what is widely considered as the next revolution for electronic packaging and hetero system integration. During the last years the manufacturing of through silicon vias has been intensely studied in Advanced Packaging and starts industrial commercialization at the moment.
15 citations
01 Jan 1998
TL;DR: In this article, the authors present an overview of the manufacturing process of substrate fabrication processes and assembly technologies, including process modelling and control, and financial affordability models for manufacturability.
Abstract: Overview. Substrate fabrication processes. Assembly technologies. Testing. Design for manufacturability. Process modelling and control. Manufacturing systems. Financial affordability models. Material properties.
15 citations
20 Oct 2011
TL;DR: The inter-die signal interfaces are shown to be well protected against CDM by placing just a small ESD protection clamp at the receiver, if certain package integration guidelines are followed.
Abstract: CDM-ESD robustness of stacked-die packages is investigated and compared with single-die packages. The peak discharge current is not increased significantly by die stacking. The inter-die signal interfaces are shown to be well protected against CDM by placing just a small ESD protection clamp at the receiver, if certain package integration guidelines are followed.
15 citations
TL;DR: In this article, a numerical method is used to determine the effective permeability for the underfilling flow domain, where epoxy encapsulant is filled into the gap between the substrate and chip by the capillary force.
15 citations