Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

A Wide Area Vertical Expansion (WAVE/sup TM/) packaging process development

Abstract: During the later 1990's, Tessera introduced a semiconductor packaging technology called WAVE (Wide Area Vertical Expansion) package to address the growing need for high pin count, high speed, high thermal dissipation, and high environmental reliability in advanced electronic packaging. The WAVE technology is an extension of Tessera's compliant packaging technologies that places a low modulus encapsulant between the silicon die and the package substrate to solve their CTE mismatch problem. The WAVE technology allows for compliant vertical interconnection links to be formed between the ICs and the substrate, with no need for a bond window. These interconnections are made simultaneously, in contrast to single point wire or lead bonding. The compliant interconnections and low modulus encapsulant enable the stress on BGA solder balls to be minimized. The WAVE package utilizes advanced materials and design to provide a unique combination of high electrical and thermal performance, high environmental reliability, and cost effective IC interconnection methodology. This paper presents one of the latest WAVE technology developments at Tessera.

Scale effect on packaging materials

Abstract: The scale effect on the typical packaging materials, underfill HYSOL(R) FP4526, FP4511 and eutectic solder alloy 63Sn37Pb is investigated in this paper. By using specially designed thin strip specimens and a computer controlled 6-axis mini fatigue tester, a series of reliable and consistent test data are obtained. It shows that the specimen scale has no significant effect on the test results within the specimen thickness investigated in this research.

On the analysis of dynamic effect in the die pick-up process

Abstract: During electronic packaging, local breakage or scratch marks on the backside of semiconductor dice are potential risks leading to failure in the subsequent packaging processes or in service. Contact-impact effect in the die pick-up process may be one of the main reasons causing the defects. To investigate the contact-impact effect, finite element analyses are performed by Abaqus/Explicit 6.8.1, considering three key factors involving impact speed, distance from the contact center and whether to penetrate the substrate or not. The conclusions are that, impact effect by ejecting needle takes effect only in limited area around the contact point and can boost local stress greatly by 8–10 times which may result in local damage to chips as observed by microscopy. Impact effect attenuates quickly with distance from the contact center. Without penetration of substrate, it does not at all contribute to the local cracking issue of chips. However, it really does with the penetration present, and the critical velocity can be evaluated using the same method as the paper. For the pick-up process, penetration should be avoided for securing the precious semiconductor chips, that is to say, tougher substrate material, right ejecting needle as well as proper velocity and height of ejecting is to be adopted.

Design, materials and process for lead‐free assembly of high‐density packages

Abstract: The High Density Packaging Users Group conducted a substantial study of the solder joint reliability of high‐density packages using lead‐free solder. The design, material, and assembly process aspects of the project are addressed in this paper. The components studied include many surface mount technology package types, various lead, and printed circuit board finishes and paste‐in‐hole assembly.