Topic
Electronic packaging
About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.
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TL;DR: In this paper, the authors investigated the effects of header shapes and the Reynolds number on the flow distribution in a parallel flow manifold to be used in a liquid cooling module for electronic packaging, and they found that the manifold flow distribution greatly depends on the header shape and Reynolds number.
98 citations
TL;DR: Two types of Moire methods are introduced and analyzed and it is shown that these systems are powerful tools for studying warpage mechanisms and can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.
Abstract: Microelectronic and photonic packaging are progressing toward integrating more devices with more functions into a smaller confined space, while requiring higher yield and superior reliability. New electronic components, materials, fabrication processes, and configurations are emerging to achieve these goals. As expected, surface flatness is playing a more crucial role in integrated circuits and integrated optics manufacturing. Out-of-plane displacement (warpage) is a global effect of interfacial stress and displacement. It is also the cause of mis-registration and noncontact between components and their substrates. Moire methods offer noncontact, full-field, high-resolution approaches for measuring warpage. In this paper, two types of Moire methods are introduced and analyzed. They carry distinct features and grant more options to measure warpage under various scenarios. It has been shown through system analysis and experimental results that these systems are powerful tools for studying warpage mechanisms. Specifically, they can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.
98 citations
TL;DR: In this article, an interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures.
Abstract: An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To achieve a smaller feature size and higher speed in future chips, SiO/sub 2/ can be replaced with low-k dielectric material in all via and trench layers or the number of metal layers can be increased. The effect of both packaging options has been evaluated. With either option, the future flip-chip copper/low-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provides a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flip-chip packages.
97 citations
IBM1
TL;DR: The surface laminar circuit (SLC) as discussed by the authors is a component carrier technology which satisfies various requirements for packaging of small computers through its surface Laminar structure, which is similar to semiconductor wiring.
Abstract: Discusses the SLC (surface laminar circuit), a component carrier technology which satisfies various requirements for packaging of small computers through its surface laminar structure, which is similar to semiconductor wiring. By utilizing photo via holes instead of plated through holes for signal line connection, SLC has a high wiring density which allows it to carry bare chips directly attached on the SLC by flip chip attach. This packaging technology has an extended reliability compared with conventional flip chip bonding and a wide range of application in small computers. >
97 citations
20 Oct 2004
TL;DR: In this article, the effect of bump defects in high-brightness LEDs has been investigated and the importance of zero defects in one of the more popular interconnect schemes; the epi down soldered flip chip configuration is investigated and demonstrated.
Abstract: The efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. Light emitting diodes, LEDs, are a strong candidate for the next generation, general illumination applications. LEDs are making great strides in terms of lumen performance and reliability, however the barrier to widespread use in general illumination still remains the cost or $/Lumen. LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents, and thus the need for lower thermal resistance packaging designs. As the power density continues to rise, the integrity of the package electrical and thermal interconnect becomes extremely important. Experimental results with high brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips leading to premature failures. A numerical study was also carried out with parametric models to understand the chip active layer temperature profile variation due to the bump defects. Finite element techniques were utilized to evaluate the effects of lo calized hot spots at the chip active layer. The importance of zero defects in one of the more popular interconnect schemes; the epi down soldered flip chip configuration is investigated and demonstrated. Keywords: High brightness LEDs, Infrared imaging, Microscopic IR, Bump defects, Finite element analysis.
96 citations