Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Aluminum Silicon Carbide (AlSiC) Thermal Management Packaging For High Density Packaging Applications

Abstract: High-density microelectronics require packaging materials and systems that provide superior thermal management and highly functional interconnection schemes for component performance and reliability. Aluminum Silicon Carbide (AlSiC) metal matrix composite (MMC) packages have a unique set of material properties that are ideally suited to thermal management performance, and a functionality that supports high density interconnection microelectronic packaging applications. Furthermore, the AlSiC fabrication and processing technology provides these high performance attributes cost-effectively. The AlSiC coefficient of thermal expansion (CTE) value is compatible with direct IC device attachment allowing for the maximum thermal dissipation into the high thermal conductivity (170 – 200 W/mK) AlSiC package. Additionally, the low material density of AlSiC (3 g/cm 3 ) makes it ideal for weight sensitive applications such as airborne, spaceborne, or portable devices. The AlSiC material and functional electronic packaging geometries are cost-effectively produced using Ceramics Process Systems (CPS) QuickSet™/QuickCast™ net-shape (without machining) fabrication process. Functional packaging features such as feedthrus, sealrings and substrates are incorporated in AlSiC during fabrication using the CPS Concurrent Integration™ technique eliminating the need for additional assembly and brazing (or soldering) operations. The ideal material properties coupled with AlSiC fabrication and Concurrent Integration™ process provide low-cost high performance functional thermal management packaging solutions. This paper will illustrate the AlSiC material/packaging capabilities through examples of High-Density Interconnect (HDI) electronic packaging, which will be discussed in terms of the ultimate component reliability. In addition the AlSiC packaging cost-efficiency will be illustrated through an outline of the AlSiC material/packaging fabrication process which will be contrasted to traditional fabrication and packaging assembly techniques.

Thermal Analysis of Solder Joint Based on Eddy Current Pulsed Thermography

Abstract: Solder joint provides electronic and mechanical connections between components and substrate. Overheating and excessive temperature gradient can cause solder joint failures and then make the whole system break down. Thus, thermal analysis has been the hotspot in reliability evaluation of electronic packaging. This paper proposes eddy current pulsed thermography (ECPT) to investigate thermal transfer through solder joint in a surface mounted device (SMD). A 3-D electromagnetic-thermal model was built, and the ECPT system was established to analyze transient temperature distribution on the pin surface. This model introduced pseudo soldering and evaluated its impacts on thermal conduction. Thermal resistance of solder joint was calculated to characterize different pseudo soldering defects. With pseudo soldering acreage increased, thermal resistance had an approximate quadratic rise. Both simulation and experimental results indicate that the surface temperature gradually decreases with the increase of pseudo soldering acreage. This ECPT method could be applied to the thermal analysis of solder joint in SMD, and it also could provide guidance for thermal design or reliability evaluation of electronic packages.

Research on deep RIE-based through-Si-via micromachining for 3-D system-in-package integration

Abstract: This paper reports the designing/simulation and experimental investigation into the Deep RIE-based micro-fabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with various sections, especially those with tapered profile. The effectiveness of the simulator is verified with process trials. Optimal deposition parameters are obtained for conformal formation of insulation, barrier and seed layers for electro-plating via filling. Combined with additives, Periodic Pulse Reverse current plating is utilized for satisfying bottom-up blind-via filling. The research have laid firm groundwork for the demonstration of the prospect of 3-D packaging based microsystem integration, combining heterogeneous micro/nano devices with ICs, in consumer, industrial and defense electronics.

Transient Plane Source technique for measuring thermal properties of silicone materials used in electronic assemblies

Abstract: Thermal conductivity represents a critical thermophysical property often monitored during the development and manufacture of new products. The Transient Plane Source (TPS) technique is a rapid and precise method for studying thermal transport properties. In the evaluation of electronic materials, information on thermal conductivity, thermal diffusivity and specific heat per unit volume is found from a rapid, single, nondestructive test of the material being studied. In this study, several silicone-based electronic materials with various fillers have been evaluated. These materials represent a typical cross section of those used in automotive electronics, general electronics and chip scale packaging. The study reviewed the methodology and techniques necessary for applying the TPS system to the analysis of silicone materials. Optimization of sensor selection, sample size, sample preparation and system parameter selections are discussed with results for each family of materials presented. The results validate the TPS technique as a rapid, nondestructive method to aid in characterizing newly developed electronic packaging and interconnect materials for both macro and micro electronic applications.

Stresses in electroless Ni-P films for electronic packaging applications

Abstract: Electroless-plated nickel films for electronic packaging applications such as under bump metallurgy (UBM) and flip chip bumps are investigated in this study. Quantitative stress of an electroless-plated Ni-P film on an Al coated Si wafer has been measured using a laser scanning profiler and the Stoney equation. A tensile intrinsic stress was developed due to plating defects, and also a tensile extrinsic thermo-mechanical stress due to temperature change and the CTE mismatch of Ni film and Si substrate was observed. It was found that the extrinsic stress became more tensile as the phosphorus content of the electroless Ni film decreased. Therefore, it is necessary to reduce the amount of stresses developed at the electroless Ni film by controlling phosphorous content of the electroless Ni film for reliable electronic packaging applications.