Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Electrochemical Migration in Multichip Modules

Abstract: Laminated substrates are used widely in the manufacture of multichip modules (MCM‐L) by the electronic packaging industry. Of late, the thrust has been towards higher density circuitry to achieve improved performance and reduced size. This has led to the use of finer lines and spacings, smaller drilled holes and buried vias in organic laminates leading to reliability issues such as electrochemical migration. One of the forms of electrochemical migration is known as conductive filament formation. Conductive filament formation is an electrochemical process. In accelerated environments of temperature and humidity, organic laminates can develop a loss of insulation resistance between conductors, eventually resulting in loss of electrical function of the circuit. The paper aims at discussing electrochemical migration in general, and conductive filament formation in particular, and its impact on the reliability of MCM‐L.

Time integration procedures for a cyclic thermoviscoplasticity model for Pb-Sn solder applications

Abstract: A semi-implicit time integration scheme has been developed for a cyclic thermoviscoplastic constitutive model with tensorial internal state variables for Pb-Sn solder, a common metallic constituent in electronic packaging applications. The procedure has been implemented numerically into the commercial finite element (FE) code ABAQUS (1995) by user-defined material subroutines. Several simulations are conducted to compare the numerical implementation to experiments including monotonic uniaxial tests at different temperatures, creep tests at four stress levels, and a test with two-step load-controlled cyclic loading for 62Sn36Pb2Ag solder. An explicit time integration scheme is used as well to compare with the semi-implicit scheme. The accuracy as well as the stability of the solutions are considered. Several suggestions are made for using the material constitutive model and the semi-implicit integration scheme for modeling solder connections. This work provides guidelines to implement user-defined material behavior into FE analyses to perform more sophisticated thermomechanical simulations for solder connections in electronic packaging applications.

New Patternable Materials for Electronic Packaging

Abstract: New inorganic-organic copolymers (ORMOCERs – ORganically MOdified CERamics) were developed as protective coatings for electronic and optical devices, as patternable insulation and passivation layers for electronics, e. g. MCM's, and as possible interconnects and waveguides for micro optics. Depending on the chemical composition and the processing parameters, their important features are low permittivity constants (eR ≤ 3.2), high bulk resistance (RD > 1016 Ωcm), high dielectric strength (ED ≤ 400 V/μm), refractive index around 1.48, optical transparency in the range of 400 – 1300 nm, and good adhesion to numerous substrates, such as Al2O3, glass, silicon, copper, aluminum, steel, polyimides, polyesters and epoxides. The materials can be applied using standard technology. They are patterned by laser direct writing, photolithographic, screen printing or embossing technologies.

Enhanced reliability of high-density wiring (HDW) substrates through new base substrate and dielectric materials

Abstract: Flame retardant glass/epoxy composite (FR4) has been extensively used as a substrate material for microelectronic packaging due to its cost effectiveness and overall performance. However, to be able to fabricate high-density wiring with microvias, and embed capacitors, inductors, resistors, and RF and optoelectronic waveguides into a single substrate, we need materials other than FR4 as a base substrate to meet the stringent warpage requirements during fabrication. Typically, these base substrate materials should have a high modulus and good planarity in addition to having a coefficient of thermal expansion (CTE) that is close to that of silicon so that flip-chips can be attached directly to the substrate without the need for an underfill. Although low-CTE and high modulus base substrate materials can result in low warpage and can eliminate the need for an underfill, they can potentially cause delamination and cracking in the interlayer dielectric. This is due to the high CTE mismatch between the base substrate and a typical polymer dielectric. This paper aims to explore a combination of a base substrate material and an interlayer dielectric material such that the warpage is minimal, the dielectric will not crack or delaminate, and the flip-chip solder joints, assembled without an underfill, will not crack prematurely during qualification regimes or operating conditions. Non-linear finite element models with a design-of-simulations approach are used in arriving at optimized thermo-mechanical properties for the base substrate and the dielectric materials to enhance the overall reliability of the integrated substrate with flip-chip assembly. It is seen that an aluminum nitride base substrate with resin-coated foil C provides the best combination against dielectric cracking, high warpage, and solder joint fatigue. The results from the models have also been validated with experimental data.

Acceleration of lifetime modeling by isothermal bending fatigue tests

Abstract: The generation of meaningful lifetime-models is a serious and time-consuming challenge throughout the field of packaging. Wherever different materials are joined, the CTE mismatch will usually lead to thermo-mechanical fatigue due to the temperature cycles during the usage of the system [1–3]. As a result, the fatigue of interconnections is the limiting factor for reliability of electronic systems [4]. Usually lifetime investigations are executed as active or passive thermal cycles using the final systems with fixed amplitudes. The main objective is rather the validation that the system will exceed a minimum threshold than the developing of a full lifetime-model. Detailed investigations are often bypassed due to time and financial limitations not realizing the future benefits of a lifetime-model, i.e. by gaining understanding of failure mechanisms and the possibility to predict them by modelling [5–9]. Especially for interfaces based on new developed and mostly insufficiently examined materials like sintered (porous) or composite with their predicted time-depending or highly anisotropic behavior, more detailed experiments are necessary to understand the physics of failure. Such results are required for the technology developing and optimization of fatigue behavior. Therefor more experiments with samples of different technology-parameters as well as different amplitudes or load-regimes are necessary to examine the stability of failure mechanisms and the damage accumulation. New concepts to conduct such lifetime investigations faster are urgently needed [5]. The idea presented in this paper is to show a suitable method to substitute lengthy thermal cycling tests by results obtained by rapid isothermal fatigue tests at different temperatures and how to establish a correlation between both of them. For now, samples based on galvanically deposited copper are used as common reference-material. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed. In conclusion, this work shows a approach for a significant acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the thermal cycling test (TCT) samples and should show the same failure mechanism. Detailed investigations are still needed to confirm an applicability of the method also to other metal layers used in the electronic packaging industry.