Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Pressure sensing in vacuum hermetic micropackaging for MOEMS-MEMS

Abstract: Packaging constitutes one of the most costly steps of MEMS/MOEMS manufacturing. Uncooled IR bolometers require a vacuum atmosphere below 10 mTorr to operate at their highest sensitivity. The bolometer response is also dependent on the package temperature. In order to minimize cost, real estate and power consumption, temperature stabilization is typically not provided to the package. Hence, long term high sensitivity operation of IR bolometric radiometers requires a calibration as function of in package pressure and temperature. A low-cost and accurate means of measuring the pressure in the package without being affected by the operating temperature is therefore needed. INO has developed a low-cost, low-temperature hybrid vacuum micropackaging technology 1-3 . An equivalent flow rate of 4×10 -14 Torr·L/sec for storage at 80°C has been obtained without getter. Even with such low flow, the long term stabilization of residual pressure variations affects the sensitivity and calibration of the IR bolometers. INO has developed MEMS pressure sensors that allow for real-time measurement of package pressure above 1 mTorr, and can be integrated with the IR bolometers in a die-level packaging process or microfabricated simultaneously on the same die. In this paper, the typical performance and measurement uncertainty of these pressure sensors will be presented along with a reading method that provides a pressure measurement with a dependence on the package temperature as low as 0.7 %/°C. Complex reading circuit or temperature control of the packages are not required, making the pressure sensor well adapted for low-cost high-volume production and integration with IR bolometer arrays.

Thermal effects of die-attach voids location and style on performance of chip level package

Abstract: Thermal characterisation of chip-scale packaged power devices is crucial to the development of advanced electronic packages for communication and automotive applications. Solder thermal interface materials (STIMs) are often employed in the packaging of power semiconductors to enhance heat dissipation from the chip to the heat spreader. However, voids formation in STIMs impedes heat flow and could result in increase in the chip peak temperature. Three-dimensional finite element analysis is employed to investigate the thermal effects of lead-free solder void percentages, locations and styles on packaged semiconductor device. The thermal resistance of each voiding case is calculated to evaluate the thermal response of the electronic package. The results show that the thermal resistance and peak temperature of electronic package can significantly increase depending on the percentage, location and style of voids. The results would assist packaging and design engineers in the characterisation of the thermal impacts of different solder void patterns.

Method and system for manufacturing electronic packaging units

Abstract: A method and system for fabricating electronic packaging units which includes feeding plural lead frames (101, 201) in spaced parallel alignment on at least two planes, using a molder (309) to form box like housing such that leads protrude into a window of the molded body for at least one device such as light emitting diode, trimming the leads with a trimmer (311) and additional packaging processes. For a light emitting device, additional packaging steps could include mounting LED's into the package (320), wire bonding (321), depositing a clear epoxy encapsulant (323) and testing (325). The molded body could include a stepped terrace for each lead frame of the package and can be molded Nylon that can withstand 300 degrees centigrade without deforming.

Experimental Study on the Reliability of PBGA Electronic Packaging under Shock Loading

Abstract: Plastic Ball Grid Array (PBGA) one of the most important electronic packaging methods, is widely used in aeronautical industry field. According to the JEDEC standard, shock tests of PBGA assemblies are conducted under different loading conditions. Several important parameters, such as the fatigue life of PBGA assemblies, the relationship between solder joint positions and fatigue life, the relationship between strain energy density and fatigue life, are analyzed based on experiment results. The failure modes of PBGA assemblies are studied by optical microscope (OM). The results show that during the shock tests, the strains of the solder joints near the center of the specimen are larger than other positions, and these solder joints are prone to form micro cracks. With the increase of the shock times, these micro cracks extend rapidly which will eventually cause the failure of the PBGA electronic packaging.

Electronic Packaging Materials for Extreme, Low Temperature, Fatigue Environments

Abstract: Electronic packaging technology has been developed to withstand extreme temperature fatigue conditions from - 120°C to + 85°C for over 1500 cycles. This temperature regime and number of thermal cycles exceeds typical military standard (MIL-STD) testing from - 55°C to + 125°C and approximately 100 cycles. Chip-on-board (COB) packaging was selected since it reduces mass (up to 98% savings) and increases functionality on a smaller surface area (as low as 40%) compared to standard surface mount packaging technology (SMT). Material combinations of different encapsulants, die attaches, and substrates for bare silicon die with 1 mil Au wire bonds were designed and continuously monitored in situ during thermal cycling. This paper will describe experimental and modeling results of surviving material combinations and key failures that occurred at various temperatures and cycle counts.