Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Wafer Level Packaging of Micromachined Gas Sensors

Abstract: This paper presents a novel approach to combine wafer level packaging (WLP) with micromachined hotplate gas-sensing elements. This concept allows liquid-tight sealing of gas sensor devices, which protects them during production (e.g., wafer dicing) and later in the application while still allowing the target gases to reach the sensing layer. The basis of the WLP is the combination of a structured Pyrex wafer with a micromachined substrate wafer. Thereafter, thick-film SnO 2 layers are deposited and stabilized before a diffusion membrane is attached, which seals the wafer stack

Ultra-thin pocket embedding package for system in package

Abstract: Proposed is a new type of packaging technology, `pocket embedding package', using selectively anodised aluminium substrate. In this technology, chips can be embedded inside aluminium substrate so that an ultra-thin and compact type of package can be achieved. A monolithic microwave integrated circuit dice with 120 mum thickness has been successfully embedded inside the substrate with a tolerance of less than 5 mum, and 300 mum of total thickness can be achieved with excellent thermal dissipation

Photodetection system and module

Abstract: One photodetection system includes a wide bandgap photodetector array (10) which is physically and electrically integrated on a flexible interconnect layer (18) including electrical connections (20), which is packaged in a manner for being electrically integrated with processing electronics (14) such that the packaging and the processing electronics are configured for obtaining and processing signals detected by the photodetector array, or which includes both the flexible interconnect layer and processing electronics packaging features.

System Design Issues for Harsh Environment Electronics Employing Metal-Backed Laminate Substrates

Abstract: Designing harsh environment electronics continue to increase in difficulty to a rapid increase in feature content while electronics packaging technologies are often providing less reliability. In addition, restricted under-the-hood airflow and integrated (mechatronic) designs are significantly increasing operating temperatures toward their maximum operating capability. To provide a cost effective design, automotive electronics designers are pursuing circuit board assemblies directly attached to a metal plate. For cost purposes, this metal plate can also be used as part of the module housing to provide protection, as well as thermal efficiency. Unfortunately, the metal backing can often further reduce component reliability due to increases in substrate coefficient of thermal expansion. The paper investigates the impact of metal attachment on component reliability as it investigates the use of several board attachment options. These analyses are compared to finite element modeling to further understand the causes of earlier failure. In addition, the impact of additional component encapsulants and conformal coatings are investigated. Because all attachment materials must meet a certain thermal performance (both initial design and long-term performance) the thermal efficiencies of these design options are investigated, as well as the delamination due to product life. Finally, failure analyses are presented and ensure that failures match expected characteristics.

FOWLP electrical performances

Abstract: Fan Out-Wafer Level Packaging (FO-WLP) has been recognized as the main electronic packaging and integration technology. It is cost effective and has good electrical performance as compared to the Silicon Interposer. Currently, there are many different versions of this FO-WLP technology being developed with the objective to increase the routing density. In order to design integrated circuit or package the electrical chip using the FO-WLP, it is essential to characterize electrical parameters. In this paper, the Redistribution Layers (RDL) first version of the FO-WLP electrical parameters and their test structures are provided.