Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Wafer-Level Parylene Packaging With Integrated RF Electronics for Wireless Retinal Prostheses

Abstract: This paper presents an embedded chip integration technology that incorporates silicon housings and flexible Parylene-based microelectromechanical systems (MEMS) devices. Accelerated-lifetime soak testing is performed in saline at elevated temperatures to study the packaging performance of Parylene C thin films. Experimental results show that the silicon chip under test is well protected by Parylene, and the lifetime of Parylene-coated metal at body temperature (37°C) is more than 60 years, indicating that Parylene C is an excellent structural and packaging material for biomedical applications. To demonstrate the proposed packaging technology, a flexible MEMS radio-frequency (RF) coil has been integrated with an RF identification (RFID) circuit die. The coil has an inductance of 16 μH with two layers of metal completely encapsulated in Parylene C, which is microfabricated using a Parylene-metal-Parylene thin-film technology. The chip is a commercially available read-only RFID chip with a typical operating frequency of 125 kHz. The functionality of the embedded chip has been tested using an RFID reader module in both air and saline, demonstrating successful power and data transmission through the MEMS coil.

Three-dimensional x-ray laminography as a tool for detection and characterization of BGA package defects

Abstract: Non-destructive examination of the layers of a built-up substrate was achieved using three-dimensional (3-D) x-ray microlaminography, with successful separation of layers as thin as 8 /spl mu/m. The same technology was used to create reconstructed images of both surface and internal details of inner solder balls in a ball grid array package soldered to a printed circuit board. Microlaminography was also used to identify bond-wire shorts in the plane of the solder resist of a ball grid array assembly, and these were subsequently verified by destructive physical analysis. This plane is 20 /spl mu/m thick and immediately adjoining a plane of copper traces; the success demonstrates the capability of microlaminography to resolve and separate very fine detail internally within IC structures. The limits of capability of this machine were also determined; it was found that a crack of approximately 5 /spl mu/m wide in a copper trace of a BGA was not detected by the machine. As an introduction, the technology and methodology of 3-D x-ray microlaminography are explained. The results from a microlaminography system adapted for failure analysis in integrated circuit packaging are presented. It is shown that such results could not be extracted by two-dimensional (2-D) x-ray or other nondestructive methods.

Trends of Power Electronic Packaging and Modeling

Abstract: A review of recent advances in power electronic packaging is presented based on the development of power device integration. The presentation will cover in more detail how advances in both semiconductor content and power advanced package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, the role of modeling is key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

System design issues for 3D system-in-package (SiP)

Abstract: Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.

Method of packaging of electro-microfluidic devices

Abstract: A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.