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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
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Patent
29 Jan 1988
TL;DR: In this paper, a circuitized flexible film semiconductor chip carrier is manufactured on a support structure used to facilitate handling of the circuitised flexible film and to facilitate heat transfer from the semiconductor chips mounted on the carrier to a heat sink which is part of the printed circuit board.
Abstract: An electronic packaging structure, and a method of making this structure, are disclosed. The electronic packaging structure comprises a full panel, circuitized flexible film semiconductor chip carrier mounted on a circuitized substrate such as a printed circuit board. A plurality of semiconductor chips are mounted on the carrier in a selected pattern, and the carrier, with the chips, is mounted on a matching pattern of bonding sites on the circuitized substrate. Preferably, the circuitized flexible film semiconductor chip carrier is manufactured on a support structure used to facilitate handling of the circuitized flexible film and to facilitate heat transfer from the semiconductor chips mounted on the carrier to a heat sink which is part of the circuitized substrate. Also, the semiconductor chips mounted on the flexible film chip carrier may be tested, and burned in, while on the support structure before the chip carrier, with the chips, is mounted on the circuitized substrate.

63 citations

Proceedings ArticleDOI
22 Mar 2001
TL;DR: In this article, a simple model was constructed to analyze the performance of both existing and predicted future thermoelectric coolers in an electronic packaging environment, and it was shown that the thermal resistance between the refrigerator and the chip is not as critical as the thermal resistances between the fridge and the ambient air.
Abstract: Utilizing refrigeration may provide the only means by which future high-performance electronic chips can be maintained below predicted maximum temperature limits. Widespread application of refrigeration in electronic packaging will remain limited until the refrigerators can be made sufficiently small so that they can be easily incorporated within the packaging. A review of existing microscale and mesoscale refrigeration systems revealed that only thermoelectric coolers (TECs) are now commercially available in small sizes. However, existing TECs are limited by their maximum cooling power and low efficiencies. A simple model was constructed to analyze the performance of both existing and predicted future TECs in an electronic packaging environment. Comparison with the cooling provided by an existing high-performance fan shows that they are most effective for heat loads less than approximately 100 W, but that for higher heat loads, fan air cooling actually yields a lower junction temperature. If the efficiency of future TECs, as characterized by ZT/sub room/, where Z is the figure of merit and T/sub room/ is room temperature, can be increased from the present value of /spl sim/0.8 to 2 or even 3, TEC performance improves dramatically, thus making them competitive for many electronic applications. Finally, one unanticipated result of the model was the realization that the thermal resistance between the refrigerator and the chip is not as critical as the thermal resistance between the refrigerator and the ambient air.

63 citations

Journal ArticleDOI
TL;DR: In this article, a series of Pb-free die-attach technologies have been identified as possible alternatives to lead-based ones for high-temperature applications, and the fabrication sequence for each system and assesses their long-term reliability using accelerated thermal cycling and physics-of-failure modeling.
Abstract: The demand for electronics capable of operating at temperatures above the traditional 125°C limit continues to increase. Devices based on wide bandgap semiconductors have been demonstrated to operate at temperatures up to 500°C, but packaging remains the major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task by prohibiting the use of certain materials, such as lead, in electronic products. Traditionally, lead has been widely used in high-temperature solder attach. In this paper, a series of Pb-free die-attach technologies have been identified as possible alternatives to Pb-based ones for high-temperature applications. This paper describes the fabrication sequence for each system and assesses their long-term reliability using accelerated thermal cycling and physics-of-failure modeling. The reliability of the lead-rich alloy was confirmed during this investigation, while early failures of the silver-filled epoxy demonstrated their inability to survive high temperatures. An empirical damage model was developed for the silver nanoparticle paste based on fatigue-induced failures. Encouraging reliability data have been presented for the gold-tin solid-liquid interdiffusion system where bond quality was demonstrated to be a critical factor in its failure mode and mechanism.

62 citations

Journal ArticleDOI
TL;DR: A silicon photonic “macrochip” system and its associated packaging that will allow dense wavelength-division multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics is reviewed.
Abstract: The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic “macrochip” system and its associated packaging that will allow dense wavelength-division multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration and packaging advances.

62 citations

Proceedings Article
01 Jan 2010
TL;DR: The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.
Abstract: Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.

61 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896