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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


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Proceedings ArticleDOI
10 Dec 2003
TL;DR: In this article, the characterization of air-cooled vapor chamber heat sink (VCHS) and liquid cooled heat sinks (LCHSs) for electronic packages with a targeted power dissipation of 140W is presented.
Abstract: Performance-driven electronic packaging demands for thermal solutions of high power dissipation such as enhanced air cooling or, alternatively, liquid cooling technologies. This paper reports the characterization of air-cooled vapor chamber heat sink (VCHS) and liquid cooled heat sinks (LCHS) for electronic packages with a targeted power dissipation of 140W. The test vehicle flip chip plastic BGA package (FC-PBGA) involves a thermal test chip with a footprint of 12mm/spl times/12mm mounted on a high density substrate of 40mm/spl times/40mm with 1296 I/Os. The VCHS for characterization consists of a copper vapor chamber attached to the base of an Aluminum heat sink. Five types of thermal interface materials were used in the characterization study. In liquid cooling testing, two Aluminum LCHSs with microchannel width around 0.2mm were designed, fabricated and assembled with the chip. De-ionized water was used as coolant. Thermal measurements were conducted and the system-level thermal analysis shows that, for the VCHS, the overall thermal resistances ranged from 0.72 to 0.61/spl deg/C/W, and maximum power dissipations around 100W are achieved given allowable chip temperature rise of 60/spl deg/C. For the liquid cooling characterization, both thermal resistances and pressure drops were obtained at different flowrates and the system thermal resistances ranged from 0.42 to 0.35/spl deg/C/W at pressure drop less than 0.1 bar, indicating the achievable power dissipation of 140 to 170W. This study reveals that there exist performance limits for the air cooling techniques and liquid cooling technique is a feasible candidate for cooling next-generation high-performance electronic packages.

57 citations

Proceedings ArticleDOI
18 May 1992
TL;DR: In this paper, the PPGA (plastic pin grid array) package supplied the required current and maintained junction temperatures at less than 100 degrees C while dissipating 150 W. This required innovation in five areas: die metalization, bondwire layout, die attach, and cooling by a thermosiphon.
Abstract: Recent developments in computer-aided design have made possible the highly automated layout of custom ECL (emitter coupled logic) circuits. These layouts have a much higher circuit and power density than gate array designs. It is now possible to place an entire ECL microprocessor, including floating point unit and cache memory, on one large die. To demonstrate the capability of supporting such a die, the authors built and tested low-cost, air-cooled single-chip packaging for a 12.6-mm*15.4-mm die. The PPGA (plastic pin grid array) package supplied the required current and maintained junction temperatures at less than 100 degrees C while dissipating 150 W. This required innovation in five areas: die metalization, bondwire layout, PPGA package design, die attach, and cooling by a thermosiphon. >

57 citations

Journal ArticleDOI
TL;DR: To demonstrate the effectiveness of the C-TSV structure for wafer-level 3D integration, feasibility study of the implementation of the novel process and mechanics comparisons of these two 3D chip stacking structures under thermal loading through finite element (FE) stress simulation are made.

57 citations

Journal ArticleDOI
TL;DR: In this article, the fabrication of integrated passive devices (IPDs) using wafer level thin film fabrication is discussed, and a brief overview of the different possibilities for the realization of IPDs using Wafer level packaging technologies is presented.
Abstract: Integrated passives have become increasingly popular in recent years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context, particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). IPDs combine different passive components (R,L ,C ) in one subcomponent to be assembled in one step by standard technologies like surface mount device (SMD) or flip chip. In this paper, the wafer level thin film fabrication of integrated passive devices (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization, as well as results from the electrical characterization will be discussed.

57 citations

Journal ArticleDOI
01 Jun 2006-JOM
TL;DR: In this paper, the effect of the addition of lanthanum on the melting behavior, microstructure, and shear strength of an Sn-3.9Ag-0.7Cu alloy was investigated.
Abstract: Severallead-free material systems are availableas replacements for traditional lead-based solders in microelectronic packaging, including near-eutectic combinations oftin-rich alloys. Although these materials have superior mechanical properties as compared to the Pb-Sn system, much work remains in developing these materials for electronic packaging. Small additions of rare-earth elements have been shown to refine the microstructure of several lead-free solder systems, thus improving their mechanical properties. This study investigated the effect of the addition of lanthanum on the melting behavior, microstructure, and shear strength of an Sn-3.9Ag-0.7Cu alloy. The influence of LaSn3 intermetallics on microstructural refinement and damage evolution in these novel solders is discussed.

57 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896