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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a unique 6-axis sub-micron thermo-mechanical fatigue tester is described, including some calibration work for both load cell and machine stiffness.

42 citations

Proceedings ArticleDOI
01 Jun 2004
TL;DR: In this article, the authors investigated the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB).
Abstract: The increasing demands on future electronic products require more efficient system integration technologies. Especially the package density gap at board level with the high integrated circuits (ICs) on the one hand and the discrete passive components on the other has to be closed by new packaging technologies which integrate the passive components into the substrate, an interposer or the IC itself. This paper presents investigations for the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB). Technologies from wafer level packaging were adapted for manufacturing of the integrated components. The examinations were carried out with special focus on integrated coils and passive filter structures. Build up, design, processing as well as results of the electrical characterization of the integrated components are described in detail. Furthermore, an integrated passive device (IPD) for application as a filter element in the Bluetooth band is presented.

42 citations

Journal ArticleDOI
TL;DR: In this article, two theoretical models have been developed to better understand the experimental findings, which can reproduce and extrapolate the experimental results, leading to a useful design rule for practical applications involving parylene C coating.
Abstract: Parylene C is a biocompatible polymer that has been investigated as an encapsulation material for implantable microsystems. Since parylene C is deposited directly on the substrate from the vapor phase it can conform to a wide range of geometries. However, the thickness of the deposited layer tends to decrease in microscale gaps, which might lead to an insulation failure. To ensure more robustness of the coating, the changes in parylene C coating thickness have been investigated experimentally using simple gaps of known dimensions. In an attempt to better understand these experimental findings, two theoretical models have been developed. The first one, which is based on a diffusion approximation, is able to reproduce and extrapolate the experimental results, leading to a useful design rule for practical applications involving parylene C coating. As an example, we present the substrate design of a flexible sieve electrode for a peripheral nerve interface. The second model aims at an appropriate microscopic description of the coating process in terms of kinetic theory of gases.

41 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a circuit model which accurately characterizes the nonideal behavior of SMD inductors mounted on a printed circuit board (PCB), considering the device packaging and the interaction between board layout and component parasitics.
Abstract: An understanding of the high-frequency parasitic and packaging effects of passive surface-mounted devices (SMDs) can be gained from equivalent-circuit characterization of the device. We develop a circuit model which accurately characterizes the nonideal behavior of SMD inductors mounted on a printed circuit board (PCB), considering the device packaging and the interaction between board layout and component parasitics. The model is valid over a wide frequency band up to the first resonance of the inductor. The equivalent-circuit parameters are extracted in closed form from an accurate measurement of the S-parameters of the board-mounted SMD inductor, without the necessity for cumbersome optimization procedures normally followed in RF circuit synthesis. This procedure of measuring the component in its designed PCB environment is referred to as extrinsic characterization, in contrast to the conventional intrinsic characterization employed in RF bridges and LCR meters, which does not include the board layout effects. The developed closed-form model can be directly incorporated in commercial CAD packages, and thus, it simplifies the analysis of electromagnetic field behavior in PCBs, such as prediction of radiated emissions, signal integrity, and EMI.

41 citations

Journal ArticleDOI
TL;DR: A wafer-scale packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.
Abstract: A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are interconnected via the wafer using standard multilevel metallization processes. The packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.

41 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896