Topic
Electronic packaging
About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.
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IBM1
TL;DR: In this paper, a 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented, and a new design methodology is proposed-discontinuity cancellation in both signal-current and return-current paths.
Abstract: A 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed was beyond the reach of conventional package designs, a new design methodology was proposed-discontinuity cancellation in both signal-current and return-current paths. The 3-D structures of bonding wires, vias, solder ball pads, and power distribution networks were optimized for the discontinuity cancellation. Two versions of four-layer WB-PBGA packages were designed; one according to the proposed methodology and the other conventionally. The proposed design methodology was verified with full-wave simulation, passive bandwidth measurement, time domain reflectometry (TDR), eye diagram measurement, and jitter analysis.
35 citations
TL;DR: In this paper, the benefits and challenges of Wafer-level packaging for integrated sensors are described, and the advantages and disadvantages of several technologies are discussed. But the authors focus on low cost packaging of integrated sensor devices is key to the ingress of silicon sensors into the consumer and industrial marketplace.
Abstract: Low cost packaging for integrated sensor devices is key to the ingress of silicon sensors into the consumer and industrial marketplace. Wafer-level packaging for integrated sensors can be performed using several technologies. The benefits and challenges of several these technologies are described.
35 citations
TL;DR: A bond-graph model of a piezostack driven jetting dispenser that can dispense adhesive fluids accurately, rapidly, and flexibly is presented.
35 citations
TL;DR: In this article, a three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications, where solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides.
Abstract: Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.
35 citations