Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

High-efficiency 60 GHZ antenna fabricated using low-cost silicon micromachining techniques

Abstract: In this paper, a miniature, multi-functional Si-based packaging technology which can reduce the size and cost and increase the performance of a wide range of millimeter wave systems is proposed. High density capacitors, low temperature coefficient resistors, high-Q inductors, low-loss transmission lines, filters and antennas can all be built within the Si package using standard semiconductor fabrication methods with very high manufacturing precision compared to conventional packaging technologies. Fine pitch metal bumps can be used to attach RF IC's and other components, while bonding can provide hermetic sealing where required. Vias through the Si package eliminates inductive bond wires and minimize parasitics at millimeter wave frequencies. By integrating both antenna and an RF IC in one single package, all high frequency signals are confined within the package and only baseband signals connected to the external package.

Mechanical characterization of plastic ball grid array package flexure using moire interferometry

Abstract: Most previous studies of PBGA packaging reliability focused on the effect of thermal cycling. However, as portable electronic products such as cellular phones and laptop computers are reduced in size and become more readily available, isothermal flexural fatigue also becomes an important reliability issue. Solder interconnects subjected to mechanically induced deformation may result in failure. In the current work, moire interferometry is used to investigate the influence of PCB flexure on interconnect strains. A versatile testing apparatus is developed to load PBGA packages in four point bending. Moire fringe patterns are recorded and analyzed at various bending loads to examine the variation in displacement and strain between the components. Solder balls across the entire array experience large shear strains, often resulting in plastic deformation, which reduces service life of the package.

Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design

Abstract: During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mmtimes10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA

Stacked thin dice packaging

Abstract: This paper reports on a developed stacking method to produce a small volume three-dimensional package. The first part of the 3/sup rd/ dimension is tackled by reducing package thickness and also the stand-off height. The steps came through thinning dice, using a thin interposer, and to stack the components. The thickness of the used ICs was 90 /spl mu/m, whereas typically thicknesses are around 250-300 /spl mu/m. Thin dice were connected through eutectic solder bumps on thin aramid epoxy substrates. The package was studied with the finite element method (FEM) using three-dimensional (3-D) models and the Ansys program. The average plastic work in the solder bump was used to define the reliability of the structure. Structures with one to four layers are compared. In current flip-chip assemblies, rigidity assists good electrical performance and reliability. Reducing the IC thickness below 100 /spl mu/m creates new challenges for handling, interconnecting, reliability and design. These tasks have been addressed in this study. The designed circuits for the above tests have been characterized and more details of the results are presented. Further progress in density increase has been achieved by stacking layers of flexible substrate and thin die on top of each other. For this work, the first level connection has been flip-chip bonding. The goal was to develop a method to produce modules on a small scale to verify the feasibility of various System-in-Package (SiP) solutions. The method has been tested using thin dice, mainly daisy chain. Devices are miniaturized to be more comfortable to carry; this size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Size reduction of electronics has set a challenge for packaging and provided the motivation to verify emerging technologies.

Motion stages for electronic packaging design and control

Abstract: This paper reviews the design and control progress of motion stages for electronics packaging, specifically, for wire bonding, due to its characteristics of high acceleration and high accuracy. The paper also introduces both conventional serial-type and new parallel-type motion stages. Several modeling techniques and many high performance control schemes are also reviewed