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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors explored the use of resorcinol based phthalonitrile (rPN) in harsh environment electronics encapsulation applications, and demonstrated the integration of the rPN hybrid polymer onto dual-in-line packages (DIPs), which did not fail when subjected to an extreme environment of 310 °C at 190ÂMPa.

34 citations

Patent
16 Jul 2008
TL;DR: In this article, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional integration applied to electronic packaging is disclosed, and an arrangement for implementing the inventive method is presented.
Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

33 citations

Proceedings ArticleDOI
23 May 2000
TL;DR: In this paper, an appropriate anisotropic spreading resistance formulation that can be used in compact models of electronic packages of printed circuit boards (PCBIs) was proposed to evaluate the thermal conductivity of these materials.
Abstract: The electronic package structure often comprises of materials that occur in thin layers In many instances, these materials are lumped Together as a simplified compact model to represent their thermal performance enabling parametric studies of the package structure This new compact structure will have a new set of thermal properties that differs from its constituent components Their combined material properties often display anisotropic thermal conductivity because layers of conductive and less conductive materials results in an orthogonal heat transfer behavior This paper addresses the analytical and numerical studies of heat spreading in an anisotropic conductivity material with particular reference to the printed circuit boards (PCB) The PCB is considered to be a single material with highly anisotropic thermal conductivity, depending on the distribution of copper planes and thermal vias The motivation for this study is to determine an appropriate anisotropic spreading resistance formulation that can be used in compact models of electronic packages

33 citations

Journal ArticleDOI
TL;DR: In this paper, a flip-chip-based self-assembly method is proposed for 3D MEMS-IC large-scale integration, where solder bumps are directly formed onto a MEMS chip using liquid solder solution in a bath.
Abstract: Nowadays, industries are investigating new, original and appropriate solutions to address challenges in 3D MEMS-IC large-scale integration. Self-assembly techniques are among those. We report on an alternative approach inspired from fluidic self-assembly and using the flip-chip method. Here, solder bumps are directly formed onto a MEMS chip using liquid solder solution in a bath. The self-alignment process is operated after surface treatment by plasma deposition to form high and low wettability selective patterns. Finally, MEMS and electronic chips are permanently bonded after low thermal heating without any pressure. Electrical contact is established and electromechanisms of the microsystems are proven. Compared to classic MEMS-IC flip-chip methods, this strategy presents many advantages: it is a low-cost and fast fabrication process requiring no specific equipment for deposition of solder bumps. Furthermore, it can be applied on different substrates and it does not require a specific pressure method during the bonding process. This strategy is also an appropriate fabrication method for large-scale MEMS integration where electronic connection density is high.

33 citations

Journal ArticleDOI
TL;DR: A study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap concludes that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and the solder bump resistance to the flow can not be neglected.

33 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896