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Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
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Journal ArticleDOI
Rao Tummala1
20 May 1990
TL;DR: In this article, the authors discuss the advanced packaging technologies that can be expected in the 1990s in high-performance systems in terms of chip connection, power distribution, heat removal, and thick-and thin-film wiring and package interconnections.
Abstract: The advanced packaging technologies that can be expected in the 1990s in high-performance systems are discussed in terms of chip connection, power distribution, heat removal, and thick- and thin-film wiring and package interconnections. The following topics are discussed in detail: (1) chip-level connection providing the required connections between the chip and the package; (2) power distribution to the chip and heat removal from the chip; (3) first-level packages providing all the necessary wiring, interconnections, and power distribution; (4) first-to-second level interconnections; and (5) second-level packages providing all the necessary wiring, connections, power distribution, and power supply connection. >

33 citations

Patent
06 Jan 2005
TL;DR: In this article, a method for encapsulating electronic components in consumer electronic devices is disclosed and a sealed packaging shell for electronic components is created from a single monolithic piece of elastomeric material.
Abstract: A method for encapsulating electronic components in consumer electronic devices is disclosed A sealed packaging shell for electronic components is created from a single monolithic piece of elastomeric material Electronic components, including a PCB, are hermetically encapsulated within the packaging shell during the process of its formation

33 citations

Patent
27 Jun 2006
TL;DR: In this paper, a 3D electronic packaging unit with a conductive supporting substrate is presented, which can achieve multi-chip stacking through the signal contacts on the both sides of the unit.
Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.

33 citations

Proceedings ArticleDOI
01 Jun 1999
TL;DR: In this article, the board-level (i.e., package to board interconnect) reliability of both 1.0 and 1.27 mm pitch PBGAs for the severe automotive environment is evaluated.
Abstract: Ball grid array (BGA) has become the mainstream package of choice for devices with pin counts greater than 160. As such, the current generation of automotive engine and electronic transmission controllers for under-hood and on-engine mounting with pin counts in the 200 to 350 pin count range are being introduced by Motorola in BGA packaging. There is also a driving force to reduce the form factor of automotive electronics, both due to space constraints and to achieve lower material costs. All this is occurring while there is a shift to put more electronics under-hood and specifically on-engine, where temperatures can be greater than typical firewall mounting. One special concern with the BGA, therefore, is its ability to withstand the repeated cycling associated with these applications up to temperatures that can approach 150/spl deg/C. This paper will outline testing and simulation using finite element analysis (FEA) that was performed to assess the board-level (i.e., package to board interconnect) reliability of both 1.0 and 1.27 mm pitch PBGAs for the severe automotive environment. Variables such as package body size, die size, ball size, package substrate thickness, solder ball pitch and the presence/absence of thermal balls will be addressed. Solder joint fatigue failure data from the commonly used -40 to 125/spl deg/C automotive thermal cycling condition as well a more severe potentially required condition of -50 to 150/spl deg/C will be presented to show the suitability of PBGA for the intended application from a solder joint reliability perspective.

33 citations

Journal ArticleDOI
20 May 1990
TL;DR: An overview of the present status and future trends in electronic packaging technologies is presented in this paper, where advanced modules packaged with these technologies are show in three major systems: switching systems, transmission systems, and computer systems.
Abstract: An overview of the present status and future trends in electronic packaging technologies is presented. Advanced modules packaged with these technologies are show in three major systems: switching systems, transmission systems, and computer systems. It is projected that high-speed digital switching modules will adopt multichip packaging because they can transmit high-speed pulses. In the latter half of the 90s, prototypes of optical switching modules will be implemented. In optical communication systems, a fine flip-chip interconnection technique using solder bumps will become indispensable for high-speed optical modules operating at over 20 GHz. As inductance corresponding to wire length degrades electrical characteristics, innovative packaging using impedance-matched film carriers will be developed for GaAs MMIC (microwave monolithic integrated circuit) modules in future microwave transmission systems. Multichip packaging will be widely used in computer systems because it provides higher packaging density, ensuring reduced interconnection delays. >

33 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896