Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Current Leads and Optimized Thermal Packaging for Superconducting Systems on Multistage Cryocoolers

Abstract: Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.

Embedded conductor technology for micromachined RF elements

Abstract: A surface-micromachined, multilayer, embedded conductor fabrication process is presented. The process is based on high-aspect-ratio MEMS via formation and subsequent conformal/plate-through-mold metallization. Using this process, the fabrication of epoxy-embedded, high-Q electroplated RF inductors is demonstrated. This process has two attractive features. First, the embedded nature of these interconnects and inductors allows conventional handling and packaging of inductor/interconnect/chip systems without additional mechanical consideration for the inductor structure and without its significant electrical degradation after further packaging. Second, since the embedding material forms a permanent structural feature of the device, embedding materials that would otherwise be difficult to remove during the fabrication process are instead very appropriate for this technology. The epoxy-based implementation of this technology is low temperature and compatible with post-processing on CMOS foundry-fabricated chips or wafers. Multiple solenoid-type inductors with varying numbers of turns and core-widths are fabricated on a silicon substrate using this technology. A six-turn solenoid type inductor shows an inductance of 2.6 nH and a peak Q-factor of 20.5 at 4.5 GHz.

Micromachined, flip–chip assembled, actuatable contacts for use in high density interconnection in electronics packaging

Abstract: Using flip–chip assembly, micromachined contacts can be used to create a high density, actuatable electronics packaging technology. Internal residual stress is used to press bimorph beam connectors upwards against a device chip. The connectors’ actuation behavior is described, including appropriate mathematical models. The electrostatically actuated beams will disconnect when driven by a 53 V signal and will reconnect when voltage falls below 43 V. Analytic models, which account for the non-linearity present in a curved cantilever beam, are presented. When switching signals, reconnection occurs in as little as 5.8 μs, disconnection occurs in as little as 4.0 μs. A microconnector’s current carrying capability can be as high as 285.3 mA and its maximum power dissipation as high as 1.47 W.

Packaging for a 40-channel parallel optical interconnection module with an over 25-Gb/s throughput

Abstract: NTT is currently working on a project aimed at developing an interconnection module which has high throughput and is both compact and cost-effective. This project is called "parallel interboard optical interconnection technology", or "ParaBIT". The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels, throughput of over 25 Gb/s, and transmission over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays also enable a packaging structure that includes transmitter and receiver in one package. To achieve super-multichannel performance, new high-density multiport Bare Fiber (BF) connectors have been developed for the optical interface of the modules. Unlike conventional optical connectors, the BF connectors do not need a ferrule or spring. This ensures physical contact with excellent insertion loss of less than 0.1 dB for every channel. A polymeric optical waveguide film with a 45/spl deg/ mirror for coupling to the VCSEL/PD arrays by passive optical alignment has also been developed. Also to ensure easy coupling between the VCSEL/PD array chips and the waveguide, a packaging technique has been developed to align and diebond the optical array chips on a substrate. This technique is called Transferred Multichip Bonding (TMB), and can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques offer the performance of an ultra-parallel interconnection in prototype ParaBIT modules.