Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Ultra CSP/sup TM/-a wafer level package

Abstract: There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP/sup TM/. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed.

Waveguide and packaging technology for optical backplanes and hybrid electrical-optical circuit boards

Abstract: Due to ever-faster processor clock speeds, there is a rising need for increased bandwidth to transfer large amounts of data, noise-free, within computer and telecommunications systems. A related requirement is the demand for high bit-rate, short-haul links. Here, optical transmission paths are a viable alternative to high-frequency electrical interconnections, whereby layers with integrated waveguides are particularly suitable. The reasons for this include that a higher connection density can be achieved and the power dissipation, as well as interference from electromagnetic radiation, are significantly lower. The article presents general considerations and the results of research conducted by the German BMBF Project NeGIT, into the manufacture of circuit boards with embedded polymer optical waveguides. The electrical-optical boards were fabricated using precise photolithographic processes and standard lamination methods. They possess the thermal stability necessary for manufacturing processes and operational conditions, in terms of both bond strength and the stability of the optical properties. As part of this project, a design of an optical coupling in the daughter card and board backplane interfaces was developed and is presented as the centerpiece of this study.

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Abstract: Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

High-frequency characterization of electronic packaging

Abstract: Preface. 1. Electronic Packaging and High Frequencies. 2. Electrical Description of Electronic Packaging. 3. High-Frequency Measurement Techniques. 4. High-Frequency Measurement Techniques for Electronic Packaging. 5. Measurement-Based Modeling Algorithms. Index.