Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

Microrelay packaging technology using flip-chip assembly

Abstract: Using flip-chip assembly, micromachined connectors can be used to create a high density, actuatable electronics packaging technology. Internal residual stress is used to press bimorph beam connectors upwards against a device chip. Deformation can be increased by introducing stress through a heat treating process. The effects of heat treatment are more prominent on larger devices and are long lasting in nature. The connectors' actuation behavior is described, including appropriate mathematical models. The electrostatically actuated beams will disconnect when driven by a 53 volt signal and will reconnect when voltage falls below 43 volts. When switching signals, reconnection occurs in as little as 5.8 /spl mu/s, disconnection occurs in as little as 4.0 /spl mu/s. A microconnector's current carrying capability can be as high as 285.3 mA and its maximum power dissipation as high as 1.47 W.

Methods to reduce radiation from split ground planes in RF and mixed signal packaging structures

Abstract: Split ground planes are sometimes used in RF and mixed signal packages in order to isolate the RF and analog circuits from the digital circuits. Undesired radiation in a packaging environment may occur when a signal trace is routed over a slot in the ground plane. This paper examines and investigates ways to eliminate signal coupling into split ground plane structures and assesses the impact of this reduced coupling on signal integrity in a packaging environment. Suggested methods to reduce coupling of energy into the slot are to alter the shape of the slot with RF chokes or corrugations.

Design optimization and reliability of PWB level electronic package

Abstract: As the Electronic Packaging industry develops technologies for fabrication of smaller, faster, economical and reliable products; thermal management and design play an important role. The major part of the failures of the electronic components is temperature related. During thermal cycling, fatigue failures are caused due to mismatch of coefficient of thermal expansion (CTE) of different materials present in the components. Increased power dissipation and density in modern electronics system require efficient and intelligent design and thermal management strategies to ensure the reliability of electronic products. This paper discusses the reliability and design optimization of a generic Printed Wiring Board (PWB) level electronic package under thermal cycle loading. Finite element tool ANSYS is used to estimate the cycles to fatigue failure of solder joint of the package coupled with optimization module present in ANSYS for providing the details on determining optimal design parameters which affect the product reliability. Combining finite element analysis with optimization would significantly reduce the design time and increases the product reliability. Four model characteristics: PWB core in-plane Young's Modulus, PWB core in-plane coefficient of thermal expansion, PWB core thickness and the stand-off solder joint height are chosen as the optimization inputs (design variables) that ensure higher reliability and improved performance of the assembled product. The objective of the optimization is to improve the fatigue life of solder joints of the package. Sub approximation, Design of Experiment (DoE) and Central Composite Design based Response Surface Modeling Methodology are used to study the effects of each design variables on the fatigue life.