scispace - formally typeset
Search or ask a question
Topic

Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.


Papers
More filters
Patent
11 Sep 2002
TL;DR: In this paper, a device for electrically interconnecting and packaging electronic components is presented, where at least one electronic component is disposed within the recess and the conductors of the component are routed through the lead channels.
Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a set of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the conductors of the component are routed through the lead channels. A set of insertable lead terminals, adapted to cooperate with the specially shaped lead channels, are received and captured within the lead channels, thereby forming an electrical connection between the lead terminals and the conductors of the electronic component(s). A method of fabricating the device is also disclosed.

29 citations

Proceedings ArticleDOI
01 Jun 2004
TL;DR: In this paper, a fabrication and packaging approach for a piezoresistive micro electro mechanical (MEMS) pressure sensor designed to operate up to a depth of hundreds of meters under harsh seawater conditions is presented.
Abstract: We report a fabrication and packaging approach for a piezoresistive micro electro mechanical (MEMS) pressure sensor designed to operate up to a depth of hundreds of meters under harsh seawater conditions. The pressure values at such depths would typically be in the range of 3000 psi and the temperature conditions would vary from as low as -5/spl deg/C to 60/spl deg/C. The sensor essentially consists of an array of silicon diaphragms 20-60 /spl mu/m in thickness with selective regions diffused with boron (p-type) that act as piezoresistors. The packaging solution involves a wafer-level and chip scale interconnection, approach taking into consideration appropriate material selection for harsh oceanic environments. The packaged pressure sensor is tested in a simulated harsh oceanic environment. Functional tests are performed in a custom-built pressure chamber, where the deep-sea water conditions were simulated (approximately depth of 1000 m). The tests demonstrated excellent mechanical integrity of the packaged device.

29 citations

Patent
28 Feb 1990
TL;DR: In this article, the authors propose to use a plurality of packaging members, especially folding members, critical for the packaging process, in order to solve the problem of producing packs of differing sizes on one and the same packaging machine.
Abstract: 1.1. Apparatus (packaging machine) for the packaging of articles of differing size. 2.1. In packaging technology, it is often necessary to solve the problem of producing packs of differing size on one and the same packaging machine. As a rule, adapting this to the different pack formats requires considerable conversion work. This in turn involves lengthy standstill phases of the packaging machine. 2.2. To make it easier for the packaging machine to be changed over to different pack formats, packaging mem-bers, especially folding members, critical for the packaging process are provided in the form of a plurality of, preferably two sets (40, 41). A particular set of packaging members is in the packaging position (43). A further (part) set is in an exchange position (44) for the exchange of individual or all packaging members for other formats. The format change is carried out in a simple way by bringing the set (40, 41) required for the particular size of the pack into the packaging position (43) as a result of a rotational or other movement. the standstill times of the packaging machine necessary for a format change are consequently minimal.

29 citations

Journal ArticleDOI
TL;DR: A proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM).
Abstract: A parallel data-communication scheme is described for interchip communication with free-space optics. We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM). Our packaging architecture is based on a modified folded 4-f imaging system that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built, supports 48 independent free-space channels with eight separate laser and detector chips, in which each chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic (OE) free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact at only 10 in.3 (∼164 cm3) and is scalable because it can easily accommodate additional chips as well as two-dimensional OE device arrays for increased interconnection density.

29 citations

Proceedings ArticleDOI
03 Feb 1996
TL;DR: In this article, a 3D packaging concept is presented that supports three-dimensional (3D) interconnect of digital electronics using a stacked multichip module (MCM) approach, which offers an order of magnitude improvement in global communication bandwidth over traditional backplane techniques.
Abstract: A packaging concept is presented that supports three-dimensional (3-D) interconnect of digital electronics using a stacked multichip module (MCM) approach. The 3-D structure offers an order of magnitude improvement in global communication bandwidth over traditional backplane techniques. This is accomplished by simultaneously reducing interconnect length (propagation delay) and dramatically increasing physical connectivity between layers of electronics. A characterization cube is described that will demonstrate the key technologies behind the 3-D packaging concept. These include synthetic diamond substrates for heat conduction, spray cooling for heat removal, double-sided multi-layer MCM interconnect, and high density connectors that support the required inter-layer signal bandwidth. Size and weight benefits of 3-D packaging are quantified in a specific application comparison. Results suggest that machines normally confined to a computer room environment can be repackaged with this technology for airborne, shipborne, or mobile applications.

29 citations


Network Information
Related Topics (5)
Wafer
118K papers, 1.1M citations
85% related
Integrated circuit
82.7K papers, 1M citations
84% related
Transistor
138K papers, 1.4M citations
79% related
CMOS
81.3K papers, 1.1M citations
78% related
Silicon
196K papers, 3M citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202331
202293
202160
2020102
2019114
201896