Topic
Electronic packaging
About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.
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TL;DR: The failure modes of power electronics devices especially IGBTs are reviewed and a FEM analysis of a multilayered IGBT packaging module under cyclic thermal loading is presented.
139 citations
TL;DR: In this paper, the Ni-Sn/Cu-Sn IMC layer growth kinetics in the joint soldered on plated Au/Ni FR-4 printed circuit board (PCB) was discussed.
138 citations
17 Jun 2007
TL;DR: In this paper, the authors present a selection of materials that are potentially suitable for use in high temperature package assembly, including die attach, substrate, interconnections, encapsulation, case, heat spreader and heat sink.
Abstract: High temperature SiC devices need the materials for device packages also capable of working at higher temperature than those for Si devices. This paper presents a selection of materials that are potentially suitable for use in high temperature package assembly, including die attach, substrate, interconnections, encapsulation, case, heat spreader and heat sink. The temperature under consideration is up to 250degC, corresponding to the need of many applications, including automobiles and aircraft.
138 citations
Patent•
21 Jun 2000TL;DR: In this paper, an ultrathin, conformal coating is made using atomic layer deposition methods, which can be used as fillers for electronic packaging applications, for making cermet parts, as supported catalysts, as well as other applications.
Abstract: Particles have an ultrathin, conformal coating are made using atomic layer deposition methods. The base particles include ceramic and metallic materials. The coatings can also be ceramic or metal materials that can be deposited in a binary reaction sequence. The coated particles are useful as fillers for electronic packaging applications, for making ceramic or cermet parts, as supported catalysts, as well as other applications.
136 citations
TL;DR: In this paper, the chip-package interaction and its impact on low-k interconnect reliability was investigated and the results indicated that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.
Abstract: Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.
135 citations