Electronic packaging

About: Electronic packaging is a research topic. Over the lifetime, 3977 publications have been published within this topic receiving 48510 citations.

System integration with eWLB

Abstract: Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies.

Reliability and Failure of Electronic Materials and Devices, Second Edition

Abstract: This well-established and well-regarded reference work offers unique, single-source coverage of most major topics related to the performance and failure of materials used in electronic devices and electronics packaging. With a focus on statistically predicting failure and product yields, this book can help the design engineer, manufacturing engineer and quality control engineer all better understand the common mechanisms that lead to electronics materials failures, including dielectric breakdown, hot-electron effects and radiation damage. This new edition will add cutting edge knowledge gained in both research labs and on the manufacturing floor, with new sections on plastics and other new packaging materials, new testing procedures, and new coverage of MEMS devices. Covers all major types of electronics materials degradation and their causes, including dielectric breakdown, hot-electron effects, electrostatic discharge, corrosion, and failure of contacts and solder jointsNew updated sections on "failure physics," on mass transport-induced failure in Cu and low-k dielectrics, and on reliability of lead-free/reduced-lead solder connections.New chapter on testing procedures, sample handling and sample selection, and experimental design.Coverage of new packaging materials, including plastics and composites

Integration of high aspect ratio tapered silicon via for through-silicon interconnection

Abstract: This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a 3-step approach has been developed and characterized which controls via depth, sidewall profile and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

Optical I/O technology for digital VLSI

Abstract: We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8 Gb/s aggregate data rate).

Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

Abstract: The advanced 3D stacking technologies are discussed in this paper. They are the microbumping in 20 /spl mu/m pitch, the basic processes of the advanced bonding processes for the high precision and the reliable interconnections, the novel technologies to encapsulate the layered microthin gaps less than 10 /spl mu/m, and the non-destructive inspection. These technologies are confirmed to realize the 3D stacked LSI structure, and it will be expanded to the advanced system packaging technologies in the near future.