Electrostatic discharge

Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Abstract: A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V. >

Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

Abstract: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products

Abstract: The high electric displacement (D>0.1 C/m2) and breakdown field (600 MV/m) in polyvinylidene fluoride based polymers suggest high electrical energy density in this class of polymers. By defect modifications which reduce or eliminate the remnant polarization in the polymer, a high electrical energy density can indeed be obtained. This paper shows that in properly prepared P(VDF-CTFE) copolymer film capacitors, an electrical energy density ~25 J/cm3 can be obtained with a breakdown field higher than 600 MV/m. The dielectric and discharge behavior of the polymer films were investigated. The results reveal that there are strong frequency dispersions in both the dielectric and discharge behavior. The dielectric constant decreases with frequency and the discharged energy density is also reduced at shorted discharge time (~1 mus) due to increased ESR for fast discharge. The results indicate the potential of this class of polymers for high energy density capacitors and suggest the need for further tuning of the polymer compositions to reduce the frequency dispersion.