Showing papers on "Encoding (memory) published in 1980"

Word endings inflection means for use with electronic translation device

Abstract: A control circuit of the present invention comprises a first memory for storing entry words, a second memory for storing a certain number of rule patterns according to which the endings of the entry words may be inflected, and an inflection control device responsive to the first memory and the second memory for inflecting the endings of the words by a particular rule pattern developed from the second memory. In another form of the present invention, an encoder is provided for encoding a word entered into first parts of coded information common to words identified as the same and into second parts of coded information having a difference dependent on the kind of the words. The equivalency between the word entered and one of entry words stored in a memory is determined using only the first parts of coded information.

Encoder between frames

Abstract: PURPOSE:To improve the quality of encoding picture by deciding a switching control signal of quantizing characteristic intended to decrease generation of information through using stored quantity of a buffer memory and a control signal before 1 frame time. CONSTITUTION:The value of an picture element of a frame delay circuit 10 is subtracted from a digital television signal input from a signal input terminal 8 and an estimated error signal between frames is obtained. A quantizing circuit 11 quantizes this estimated error signal and outputs with the use of a buffer memory 13 by smoothing. A unatizing characteristic setting circuit 15 sets a quantizing characteristic signal by the stored quantity of the buffer memory 13 and a quantizing characteristic control signal of 1 frame time which is the output of a frame delay circuit 16. Then, the characteristic of the quantizing circuit 11 is decided. When stored quantity of the buffer memory 13 is large, the quantizing characteristic is made rough and when it is small, the characteristic is made fine.

Domain of processing and recognition memory for shapes

Abstract: An experiment concerning recognition memory for shapes investigated the consequences of manipulating the component operations of domain of processing, that is, encoding strategy, processing time, and stimulus compatibility. It is established that semantic encoding and long processing time facilitated recognition performance for low-, but not for high-, compatibility shapes. A visual task interfered with recognition memory for low-compatibility shapes. Several theoretical contributions to the domain-of-processing framework, which follow from the findings of this experiment, are presented and discussed.

Facsimile signal transmission system

Abstract: PURPOSE:To realize an accurate picture regeneration even in case the scanning time may be changed with every scanning line by reading out the time T required for recording from the picture signals equivalent to one scanning line and then carrying out encoding of the picture signal in the time longer than time T CONSTITUTION:The picture signals equivalent to one scanning line which are read out at signal reading part 1 are code-converted through encoder 2, and at the same time the necessary recording time is calculated at record time measurement part 10 When the encoding of the picture signals is over through encoder 2, the code is sent to buffer memory 3 The code is then read out from memory 3 with a fixed speed and then sent to the circuit Memory rest amount monitor part 4 discontinues the encoding action when memory 3 becomes close to its overflow state, and then gives a command to transmit the idle dummy code At receiver R the code sent from circuit 6 is memorized in buffer memory 7, and the code is drawn out according to the memorizable speed with every scanning line As a result, an accurate picture regeneration is possible even though the record scanning time may be changed

Memory access system of multiprocessor system

Abstract: PURPOSE:To make it possible to make programs of all processors equal to one another, by using a bus exclusive right signal or a bus exclusive permission signal to designate the address space of a memory. CONSTITUTION:Now, if processor 2 is in the memory access enable state, register 6 accesses the memory space in the address of an area corresponding to processor 2 according to the address signal from processor 2 because the flag signal of address register 6 becomes 0. If processor 3 is in the memory access enable state, the flag signal to register 6 becomes 1, and consequently, register 6 accesses the memory space in the address of an area corresponding to processor 3 according to the address signal from processor 3. For the flag signal of register 6, a bus exclusive right signal or a bus exclusive permission signal itself is used in case of two processors, and a signal obtained by encoding these signals is used in case of three or more porcessors.

Complex Learning and Memory

Abstract: This chapter describes complex learning and memory in humans. Learning and memory involve a complex set of processes by which experiences alter the nervous system in ways such that the changes endure and effect subsequent experience and behavior. Memory does not consist simply of responses made during learning. Humans readily learn and perform skills such as language in which responses occur in novel sequence. The memory can be indicated by speaking, dialing, pushing buttons or in other ways, such as writing or simply identifying the sequence of numbers as the correct number. The memory is formed rapidly, is usually transient, but, with rehearsal or repetition, can become long-lasting. This chapter reviews approaches to the neurobiological bases of memory. The chapter discusses the effects of brain lesions on retention and neurobiological correlates of memory.

Integrated latch circuit

Abstract: PURPOSE:To enable to remarkably reduce the number of latch circuits to X+Y circuits when the value of N is greater, by encoding, latching and decoding so that X+Y can be minimized at N=X.Y when the number of input and output terminals is N. CONSTITUTION:The decoding circuit 55 is provided to produce the output corresponding to 3X4=12 sets in response to the information of 7 sets of memory circuts 54. The signal corresponding to the output terminals T1-T12 of 12 sets, is converted into the signal having the weight of three types a-c and four types d-g at the encoding circuits I and II, each is stored to seven sets of memory circuits 54, and the output A-C and D-G are fed to the decoding circuit 55, the output is obtained as 12 types of signals AD, AE...CF, CG corresponding to the input and output, they are positively fed back to the input via the output circuit 51, and the output corresponding to the inputs can be obtained at 12 sets of terminals T1-T12. That is, the latch circuits required to obtain 12 sets of input and output terminals can be seven, and this means the number is smaller than conventional circuits by as many as five.