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Showing papers on "Encoding (memory) published in 1981"


Journal ArticleDOI
TL;DR: A process model of single-trial free recall which conforms to the constraints imposed by convolution and correlation is presented and some of the strengths and limitations of the model are discussed and contrasted with those of other models of free recall.

91 citations


Journal ArticleDOI
TL;DR: A coding theorem is established for a trellis encoding of a stationary and ergodic source over a discrete memoryless noisy channel which shows that such communication systems can perform arbitrarily close to the source distortion-rate function evaluated at the channel capacity.
Abstract: In a trellis encoding communication system the decoder is a time-invariant nonlinear filter with finite memory (sliding-block code), and the encoder is a trellis search algorithm matched to the decoder. A coding theorem is established for a trellis encoding of a stationary and ergodic source over a discrete memoryless noisy channel which shows that such communication systems can perform arbitrarily close to the source distortion-rate function evaluated at the channel capacity.

88 citations


Journal ArticleDOI
TL;DR: Patients treated with 1-desoamino-8-D-arginine vasopressin (DDAVP), a synthetic analog of the hypothalmic peptide arginine vasOPressin, demonstrate cognitive enhancement by facilitating access to semantic memory structures that are part of long-term memory.

71 citations


Patent
18 Sep 1981
TL;DR: In this paper, a method and system for encoding key product information in semiconductors is described, which is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices.
Abstract: A method and system for encoding key product information in semiconductors is disclosed. The invention is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices. A plurality of read only memory cells are juxtaposed on a semiconductor die with the circuitry which performs the primary function of the chip. The read only memory cells are interconnected with the primary circuit in such a manner that the information stored therein can be accessed only when such access does not interfere with the operation of the primary circuit. Important product information is stored in the ROM cells such as manufacturer, mask set, and other manufacturer-related information, as well as key circuit parameters such as supply voltages, operating currents, programming voltages, programming pulsewidths and the like.

30 citations


Book ChapterDOI
01 Jan 1981
TL;DR: This chapter presents several information-processing models of memory and discusses three aspects of memory: (1) encoding, (2) storage, and (3) retrieval; whether these three components truly represent distinct, independent components of the overall information- processing sequence remains to be seen.
Abstract: This chapter presents several information-processing models of memory and discusses three aspects of memory: (1) encoding, (2) storage, and (3) retrieval. The distinctions among these three elements, or components of the overall memory process, seem to permeate most models of memory. The distinctions among encoding, storage, and retrieval do not belong to, or characterize, a single theoretical orientation or model. The distinctions among these components have been enormously helpful in stimulating and clarifying our thinking about some very complicated mental events. However, whether these three components truly represent distinct, independent components of the overall information-processing sequence remains to be seen. It is characteristic of separate-store models to propose two or more separate and distinct memory stores. According to the Waugh–Norman model, perceived items enter a limited capacity primary memory (PM). Rehearsal will maintain items in PM and may contribute to their transfer to a more permanent secondary memory. The Atkinson–Shiffrin buffer model is a three-component model: (1) sensory register, (2) short-term store, and (3) long-term store.

24 citations


Patent
28 Sep 1981
TL;DR: In this article, a real-time fault-tolerant hardware error correction device is proposed, which is typically implemented as a data transfer circuit between a disc memory and a processing unit.
Abstract: The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as a data transfer circuit between a disc memory and a processing unit. It operates in two modes: as an encoding system and error detector on a disc write, and as a decoding system and error corrector on a disc read. In its first mode, each block of data from the processing unit is encoded with an error syndrome as it is transmitted to the disc memory. Two identical linear feedback shift registers (LFSR's) are used for error detection purposes. In its second mode, the same two LFSR's are implemented with a buffer memory to achieve real-time error correction. Data flow to the LFSR's from the disc memory is alternated block-by-block, one block being received by one LFSR and the succeeding block being received by the other LFSR. At the same time that data is channeled to a particular LFSR, it is channeled synchronously to the buffer memory. While one LFSR is decoding the incoming block, the other LFSR is providing output signals to correct the previous data block which is leaving the buffer memory as new incoming data arrives.

22 citations



Patent
28 May 1981
TL;DR: In this article, a second level of polycrystalline used for resistors outside the ROM was used as the encoding mask, which was later used as a mask for the encoder.
Abstract: A method of making a ROM and encoding it late in the method. Encoding is by ion implantation. A second level of polycrystalline used for resistors outside the ROM is used as the encoding mask.

15 citations


Journal ArticleDOI
TL;DR: A computer simulation that tests some of the recent proposals of semantic networks and spreading activation models of human memory is presented, andSimulations of sentence encoding, verification, and recall are presented.

12 citations


Proceedings ArticleDOI
29 Jun 1981
TL;DR: Two algorithms designed to optimize memory size and controller performance for a microprogrammed controller, including the Autonomy algorithm, which identifies data path elements which should be controlled directly from the microword without encoding.
Abstract: This paper describes two algorithms designed to optimize memory size and controller performance for a microprogrammed controller. The algorithms accept two inputs: a set of interconnected registers and logical operators called the data paths, and a control flow graph which describes how these data paths are to be exercised. The Autonomy algorithm identifies data path elements which should be controlled directly from the microword without encoding. This algorithm aids the effectiveness of the subsequent encoding algorithm by eliminating some signals from consideration. A second algorithm, the Attraction algorithm, determines which microoperations will execute in parallel and which will be encoded into separate microinstruction formats. This algorithm accepts a microword width constraint and implements parallel operations in the microcode and the corresponding encoding. Both the parallelism and the encoding are determined by the algorithm. Application of these algorithms to an example, the PDP (FOOTNOTE: PDP is a registered trademark of Digital Equipment Corporation.)-11/40, has produced a control store design 14 percent wider and equal in parallelism to an equivalent portion of the human design.

10 citations


01 Jan 1981
TL;DR: A submitted manuscript is the version of the article upon submission and before peer-review as discussed by the authors, while a published version is the final layout of the paper including the volume, issue and page numbers.
Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

Patent
24 Nov 1981
TL;DR: In this paper, a simple system for simultaneous raster scan display of video and alpha-numeric data on a single screen with provision for periodic image refreshment is presented, which includes means for encoding the electrical signals representing the spatial intensity distribution of the video signal and the alpha numeric signal.
Abstract: This invention provides a simple system for simultaneous raster scan display of video and alpha-numeric data on a single screen with provision for periodic image refreshment. It includes means for encoding the electrical signals representing the spatial intensity distribution of the video signal and the alpha-numeric signal. The coded signals are stored in a single bit map memory at the desired addresses. For display, the information is simply read from the memory through a single digital-to-analog convertor.

Patent
16 Jun 1981
TL;DR: In this paper, a method for use in an electronic digital signal processing system for improving execution time in locating requested programs, reducing program storage requirements in memory and improving packaging and repackaging of programs on direct access memory devices for the library.
Abstract: A method for use in an electronic digital signal processing system for improving execution time in locating requested programs, reducing program storage requirements in memory and improving packaging and repackaging of programs on direct access memory devices for the library. A program data set for a system is formed to recognize the references to character program names and to resolve those references into control section identification codes. Each referenced character program name is uniquely encoded to a 16 bit control section identification code used as an input to a table lookup routine. The encoded control section identification for the program library loaded on the direct access memory consists of a data set number, a module index number and a control section number. A similar data structure is used to locate programs in storage by program management once they have been retrieved from the program library stored on a direct access memory device of the system.

Patent
25 Mar 1981
TL;DR: In this article, the difference between the picture element value of a digitalized input picture signal and the outputs of respective frame memories is subtracted by respective subtractors, and a difference comparator is used to compare the absolute values of outputs from the subtractors and changes over switching circuits 7, 8 to the subtractor whose absolute value is smaller.
Abstract: PURPOSE:To encode between frames always with high forecasting precision in two frame memories and to improve encoding efficiency by changing appropriately the output of one frame memory of which forecasting error value is smaller than that of the other. CONSTITUTION:A back picture is written in the 1st frame memory 2 and an input picture preceding by one frame is written in the 2nd frame memory 4. The difference between the picture element value 1 of a digitalized input picture signal and the outputs of respective frame memories 2, 4 are subtracted by respective subtractors 3, 5. A difference comparator 6 compares the absolute values of outputs from the subtractors 3, 5 and changes over switching circuits 7, 8 to the subtractor whose absolute value is smaller. The output of the switching circuit 7 is quantized and variable length encoded by a quantizing circuit 9 and a variable length encoder 11. A control signal indicating the status of the switching circuits 7, 8 is generated by a control signal generator 12 and the control signal and the output of the variable length encoder 11 are multiplexed by a multiplexer 13 and the multiplexed signal is sent through a buffer memory.

Journal ArticleDOI
Kanai1
TL;DR: This correspondence shows one method to improve the reliability of the address encoder by encoding a virtual memory address together with data to an error correcting code.
Abstract: In a memory system with skewing reconfiguration, a virtual memory address is encoded by an address encoder to avoid using a faulty memory area. This correspondence shows one method to improve the reliability of the address encoder by encoding a virtual memory address together with data to an error correcting code. Only a few additional gates are required for the implementation if the memory system has already employed an error correcting code.

Patent
21 Nov 1981
TL;DR: In this article, a picture signal encoding system with a simple hardware constitution and suitable for high speed encoding was proposed, by encoding picture signal through compression with the MH or MR system, where the reference line before one line storing the change point in the absolute address form from the memory 2 and the present code line are read out, processed at the MPU 4 and given as the address of the table 6.
Abstract: PURPOSE:To obtain a picture signal encoding system having the conventionality with a simple hardware constitution and suitable for high speed encoding, by encoding picture signal through compression with the MH or MR system. CONSTITUTION:In case of the MH system, an encoded line stored in a picture signal buffer memory 2 is read out, an absolute address of the encoded line is converted into the line length number of white and black lines through the operation processing at an MPU4 and outputted as an address of an encoded ROM table 6 in which the MH code and the bit length are stored. An output from the table 6 is converted into the MH code with an effective bit length at the MPU4, sequentially written in a memory 8 and outputted at a P/S conversion circuit 7 for parallel/series conversion. In case of the MR system, the reference line before one line storing the change point in the absolute address form from the memory 2 and the present code line are read out, processed at the MPU 4 and given as the address of the table 6, allowing to obtain the MR code.

Patent
07 May 1981
TL;DR: In this paper, the authors propose to give an announcement of the name of the broadcast station by the coincidence signal between the reception frequency and the memory frequency in the memory of RAM constitution.
Abstract: PURPOSE:To facilitate a channel selection and at the same time prevent the misoperation, by giving an announcement of the name of the broadcast station by the coincidence signal between the reception frequency and the memory frequency in the memory. CONSTITUTION:The memory MM of RAM constitution contains the region MA to store the frequency of the broadcast station and the region MB to store the name of the broadcast station in the form of the binary code. And the writing is performed by the address control part AC, the input control circuit IC1 in the region MA and the input control circuit IC2 to the region MB each. The key unit KU contains the alphabet keys and the figure keys, and the name of the desired broadcast station is preset to the memory MM through the key encoding circuit EC. The coincidence circuit J compares the value of the reception frequency memory circuit DB with the frequency of the region MA in the memory MM and then delivers the detection signal when a coincidence is obtained. The aural output control circuit OC delivers the contents of the region MB to the aural compounding circuit VC according to the coincidence signal and also performs a control of the aural output. The display unit DSP2 for the name of broadcast consists of the dot matrix display unit and is driven by the display driving circuit DSC2 for display.

Journal ArticleDOI
TL;DR: The Buried-Subcarrier color signal encoding and decoding system was developed specifically for the RCA VideoDisc.
Abstract: The Buried-Subcarrier color signal encoding and decoding system was developed specifically for the RCA VideoDisc.

Patent
03 Sep 1981
TL;DR: In this paper, the authors propose to make a fraction of the memory area minimum even if it is used discontinuously as time, and elevate the working efficiency, by using a memory area after dividing it into plural parts by a prescribed fixed data length and also chaining them, in case when an encoding signal is inputted to the memory device.
Abstract: PURPOSE:To make a fraction of the memory area minimum even if it is used discontinuously as time, and elevate the working efficiency, by using the memory area after dividing it into plural parts by a prescribed fixed data length and also chaining them, in case when an encoding signal is inputted to the memory device. CONSTITUTION:An encoding signal is inputted and outputted to the memory 3a through the input/output ports 11-14, and each port 11-14 is connected to the memory 3a by means of time division by utilizing a time when the encoding signal VD reaches the number of transfer unit bits of the memory 3a. Accordingly, each input/output port 11-14 can all be operated at the same time. Also, when the transfer speed is enough by increasing the number of input/output ports, plural scanning read part, scanning record part, transmission part, receiving part, etc. can be set. The input/output ports 11-14 are all controlled by the port control circuits 15-18, the sequence of all the pages and the start strip of each port controlling circuit 15-18 are controlled by the central processing unit 22, and the central processing unit is operated in accordance with a command from the system controlling device 10.

Journal ArticleDOI
TL;DR: The authors investigated the effect of temporal cues on recognition performance and found that temporal cues have a retrieval function in recognition memory, however, in a second experiment, d' and reaction time measures indicated that the temporal cues do not benefit recognition performance.
Abstract: The effect of temporal cues on recognition performance was investigated. Subjects were given two lists of words to learn. In a yes-no recognition paradigm, some test words were preceded by time-of-learning cues. Initial results seemed to provide some support for the hypothesis that temporal cues have a retrieval function in recognition memory. However, in a second experiment, d' and reaction time measures indicated that temporal cues do not benefit recognition performance. The relevance of these results to some models of memory is discussed.

Patent
14 Apr 1981
TL;DR: In this paper, the authors propose to increase a data input and output speed by storing a large amount of picture data by transferring original picture data between a main memory and a data compressing and expanding device, and compressed picture data with an auxiliary memory.
Abstract: PURPOSE: To increase a data input and output speed by storing a large amount of picture data by transferring original picture data between a main memory and a data compressing and expanding device, and compressed picture data between the data compressing and expanding device and an auxiliary memory. CONSTITUTION: When the command to store binary picture information in a magnetic disk device 12 is supplied from a CPU4 to a data compressing and expanding device 6 and a magnetic disk controller 11, the data compressing and expanding device 6 read picture data successively out of a main memory 5. The read picture data is compressed by linear run-length encoding processing and the resulting data is transferred to an FIF07. When the (n)-bit data is received, the FIF07 returns an indication for interrupting succeeding data transfer and data compression processing to the data compressing and expanding device 6. COPYRIGHT: (C)1982,JPO&Japio

Patent
23 Jun 1981
TL;DR: In this article, the clock frequency produced at a generation circuit is fed to a frequency division circuit and a counter in a control circuit 10 to form an address signal 12 which selects the memory address of a memory device 13.
Abstract: PURPOSE:To avoid the disturbance of sound and to enable to record a music with an arbitrary length, by using a semiconductor memory device of cell drive and producing the melody electronically. CONSTITUTION:The clock frequency produced at a generation circuit 9 is fed to a frequency division circuit and a counter in a control circuit 10 to form an address signal 12 which selects the memory address of a memory device 13. A digital signal 14 encoding the music sound read out from the memory device 13 and the frequency signal being the base of the music sound fed from the control circuit 10 are input to a synthesis circuit 15 to synthesize the music signal, which is amplified at an amplifier 16, and converted into sound at a speaker 17 to produce a melody tone 7.

Journal ArticleDOI
TL;DR: A simple model of a bursty source is studied with the objective of understanding the relationship between coding efficiency and delay, and it appears that as the source becomes less bursty, delay grows without bound.
Abstract: A basic property of data sources in interactive applications is burstiness, i.e., short periods of activity followed by long idle periods. In these same applications message delay is the primary performance criterion. The combination of bursty flow and a delay criterion leads to a source encoding problem in which delay plays a central role. A salient feature of this problem is that there is a tradeoff between delay and the number of protocol bits required to represent the state of the source. A simple model of a bursty source is studied with the objective of understanding the relationship between coding efficiency and delay. Two encoding schemes, a block encoding technique and a technique employing flags, are examined in some detail. For both the block encoding and the flag schemes, a significant result is that as the source becomes less bursty, delay grows without bound. This result is obtained in spite of the fact that both schemes are reasonable and in the limit the encoding problem disappears. It also appears that the flag encoding technique has much smaller delay than block encoding.


Patent
26 Nov 1981
TL;DR: In this paper, the character pattern corresponding to the characters is retrieved from a character pattern generator and stored in a display memory, and the content of the display memory is displayed on a CRT display device via a picture signal synthesizing circuit.
Abstract: PURPOSE:To improve transmission density and speed, by converting character information into character codes, and encoding the run length of graphic information with variable length code. CONSTITUTION:Kana (Japanese syllabary) are inputted from a keyboard 3, the character pattern corresponding to the characters is retrieved from a character pattern generator 5 and stored in a display memory 10. The content of the display memory 10 is displayed on a CRT display device 12 via a picture signal synthesizing circuit 11. Further, the picture pattern from a picture original input processor 7 is stored in the display memory 10 and displayed on the CRT display 12 with edited characters superimposingly. Further, the read picture pattern is converted into consecutive information of variable length code and stored in an information storage memory 16 after compression.


Journal ArticleDOI
TL;DR: An error-free digital image encoding method is presented which has the format and data compression characteristics of run-length encoding, but allows for the determination of original image co-ordinates of pixels in runs without reconstruction of the image in two-dimensional matrix form.
Abstract: An error-free digital image encoding method is presented which has the format and data compression characteristics of run-length encoding, but allows for the determination of original image co-ordi...